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Found 14 results

  1. lukap

    I2S IP core and AXI DMA

    Hello. I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github. I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I understand how the DMA works. I'm basing my code on the Xilinx' interrupt DMA example, so I think the initializations and similar are done correctly. What I'm unsure of is the following: I start the S2MM (Stream to Memory Mapped - I2S to RAM) transfer with the number of bytes to be transferred and expect the I2S controller to only output data when it has it (similarly as in the Zybo base system example, except that there the fifo status register is checked, but for the streaming interface I expect this to be taken care of in the IP). So if I want to transfer 5 seconds of audio, I start the transfer of 5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample For now I then wait for the interrupt in which a flag is set, so that I know the transfer has finished. I expect this to last 5 seconds but instead it happens in a couple hundred ms (I don't have an o-scope) and only a few samples arrive. So is my understanding correct? Has anyone ever tried interfacing the I2S core to an AXI DMA?
  2. I'm designing an application using the Audio CODEC of the Zybo Z7. I'm configuring the CODEC by I2C properly and could see data coming from the I2S. Then I realized that each time I programmed the FPGA, the Led 5 of the board was turning ON... even this LED is not at all part of my design!! Never mentioned in my constraints and never mentioned in the verilog wrapper. Then proceeding by elimination when analyzing the constraints, I realized that this LED was turned ON as soon as the I2S clock went enabled... with below constraints: NO LED TURNED ON ##I2S Audio Codec ##set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK ##set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK ##set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC ##Audio Codec/external EEPROM IIC bus set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA But with below constraints enabling the CLOCK... I get the LED turning on in Red, Green or Blue depending... ##I2S Audio Codec set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC ##Audio Codec/external EEPROM IIC bus set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA I'm respecting the pin allocation proposed in the Zybo Z7 manual... therefore I do not understand what is going on... Let me know if someone already faced this situation or have any idea of the phenomena. I"m using Zybo_Audio_Ctrl IP for the I2S below a copy of my design...
  3. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 (24bit@48k), I2S output. DAC will be CS4390 (24bit@48k), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  4. Hello everyone! I am broadcast audio engineer (ex Harman Pro/Studer) with decent experience of complex audio/control systems and DIY enthusiast with Arduino and Raspberry type-of-toy knowledge:) I also can code PHP (Yii/Laravel), a bit of Python and .NET (WPF, Core and Web Forms). Component level repairs were more of a childhood game, but smell of flux was always somewhere near.. This time i have a goal to get familiar with FPGA world, so here I am and immediately starting a new thread regarding my project:) Cheers!
  5. I am trying to interface a MEMS microphone ICS-52000 with the Digital Discovery board. The microphone outputs data using Time Domain Multiplexed (TDM) signaling. TDM is somewhat similar to I2S but without the left and right channel. The Digital Discovery board has I2S listed under Logic. I want to make a Protocol for TDM. Is it possible to use the Digital Discovery board to develop a protocol that will generate a clock signal (output) along with a word select (output) synchronous to the clock signal and then read data (input) from a connected microphone? Data would be streamed to a file. Thanks, Douglas
  6. Krelle52

    Zybo DMA Audio Demo - Documentation

    I am doing a project with some audio DSP. For this I am using the audio codec on the Zybo. The first thing I want to do, is to be able to record and playback audio with a little delay between input and output. In order to speed up the development process, I decided to use the DMA Audio demo. But I'm lacking some information or rather some documentation. So is there any of your guys who knows which registers is references to here (Audio controller registers) in the code below. Since I2S is an hardware interface standard, so there should not be any registers. So I think it has something to do with DMA. But I can't find any documentation, which fits. Do anybody know which documentation would give a insight to the registers? #define AUDIO_CTL_ADDR XPAR_D_AXI_I2S_AUDIO_0_AXI_L_BASEADDR //Audio controller registers enum i2sRegisters { I2S_RESET_REG = AUDIO_CTL_ADDR, I2S_TRANSFER_CONTROL_REG = AUDIO_CTL_ADDR + 0x04, I2S_FIFO_CONTROL_REG = AUDIO_CTL_ADDR + 0x08, I2S_DATA_IN_REG = AUDIO_CTL_ADDR + 0x0c, I2S_DATA_OUT_REG = AUDIO_CTL_ADDR + 0x10, I2S_STATUS_REG = AUDIO_CTL_ADDR + 0x14, I2S_CLOCK_CONTROL_REG = AUDIO_CTL_ADDR + 0x18, I2S_PERIOD_COUNT_REG = AUDIO_CTL_ADDR + 0x1C, I2S_STREAM_CONTROL_REG = AUDIO_CTL_ADDR + 0x20 };
  7. zoggx003

    Zybo audio codex setup

    I am currently trying to setup the ssm2603 audio codex on the zybo board to output audio, with a purely rtl design. I am having issues setting up the audio codex via i2c. I am wondering about how you should send the address information to the audio codex to initialize the setup registers. Below is an RTL state machine of how I am trying to write the register values to the codex. Can someone verify that this is the correct way to address the registers? I am unable to get anything out from the audio codex currently, and I don't think my initialization is working. always @(*) begin next_state = IDLE; address = 7'h0F; data = 8'hFF; case(state) IDLE: begin start = 0; address = 7'h0F; data = 8'hFF; next_state = (setup_audio_codex) ? WR_POWER_MGNT : IDLE; end WR_POWER_MGNT: begin start = (busy) ? 0 : 1; address = 7'h06; //power management data = 8'b00000111; //PWROFF,CLKOUT,OSC,OUT,DAC,ADC,MIC,LINEIN next_state = (ready) ? WR_DIG_AUDIO_IF : WR_POWER_MGNT; end WR_DIG_AUDIO_IF: begin start = (busy) ? 0 : 1; address = 7'h07; //digital audio I/F data = 8'b00000010; //BCLKINV,MS,LRSWAP,LRP,WL,FORMAT next_state = (ready) ? WR_DIG_AUDIO_PATH : WR_DIG_AUDIO_IF; end WR_DIG_AUDIO_PATH: begin start = (busy) ? 0 : 1; address = 7'h05; //digital audio path data = 8'b00000000; //HPOR,DACMU,DEEMPH,ADCHPF next_state = (ready) ? WR_ANA_AUDIO_PATH : WR_DIG_AUDIO_PATH; end WR_ANA_AUDIO_PATH: begin start = (busy) ? 0 : 1; address = 7'h04; //analog audio path data = 8'h00010010; //SIDETONE_ATT,SIDETONE_EN,DACSEL,BYPASS,INSEL,MUTEMIC,MICBOOST next_state = (ready) ? IDLE : WR_ANA_AUDIO_PATH; end endcase end
  8. kumards

    Pmod i2s with internal SCLK

    Hello All, I tried the program given in but there is no output on the SD. I have simulated the clock with 100MHz and got these values. clk 10ns 100Mhz Sclk 1.56Mhz mclk 40ns 25Mhz SD is always zero in-spite of setting the input data_l and data_r as Ones as shown in picture and simulation output files. I am unable to find the cause for the problem. Am i missing anything in testbench code, as I am simulating only CLK ? What changes are to be made in that code if i have to use internal SCLK. I have a PCB in which is spartan 6 FPGA is hardwired to CS4344, leaving SCLK as open/NC. I tried commenting SCLK signals and ran program but it didnt help either. Kindly help to resolve. Thanks in advance. Kotresh Kumar isim for i2s.wcfg
  9. Mehdim

    How to use Audio on Zybo board

    Hello guys; Can you refer me to a quick guide about how to use Audio signal on ZYbo board? I just want to know if there is any simple tutorial about how to get data from audio jack and have in on Arm side. Appreciate your comments in advance.
  10. After trying about everything I could think of, I am still not able to produce any sound through the DAC on the Zybo's audio chip. I tried initializing the chip via I2C using what I think are the proper register values and the proper power on sequence, both using a core I wrote myself, and alternatively by connecting the I2C interface through to the Processing System and using Linux and i2c-tools there to set the register values from the command line. My initialization sequence includes activating the digital core (R9), enabling the DAC by setting DACSEL, unmuting the DAC, powering on both before (without Out) and after (with Out) setting the other registers and with the proper delay, and many more things. I am also pulling the active-low MUTE pin high using "i2c_m_mute <= '1';" in VHDL. I can make the chip pop and hiss by powering it on, and I think I can manage to put Line In or Mic onto the output with the right register values (not entirely sure since I had no Mic laying around, but I'm relatively sure I heard something when I improvised with some ear buds). Overall, there's strong indication that my initialization sequence is at least partially successful, but the DAC remains entirely silent. For the I2S signals, I have a 12.288MHz MCLK fed by a Clock Wizard, a 48kHz PBLRC clock, a 3.072MHz BCLK (for 64 cycles per 48kHz sample, but I also tried using half of that since I am only trying to feed 16bit data) and PBDAT aligned to that. I verified both with an ILA core and with an oscilloscope directly at the chip pins that the signals are there and look sound. Yet I cannot even make the chip produce anything digitally. Even if PBDAT is screwed up, it should at least produce some sort of random noise or clicking, no? What am I missing? Since I'm very new at FPGAs, this may be something entirely obvious. Attached is an example of what is going on on the I2S wires. I tried at least left justification and the I2S format. This is with a BCLK for 32 bits per sample (i.e. 16bit per channel), as mentioned above I also tried using a 64bit BCLK with no effect.
  11. Kampi

    Audio with PmodI2S with ZYBO

    Hello, I receive my I2C Audio PMOD ( today and I want to use it with my ZYBO. My I2S transmitter look like this: library ieee; use ieee.std_logic_1164.all; entity I2S_Transmitter is generic ( DATA_WIDTH : integer := 32 ); port ( Clock : in STD_LOGIC; MCLK : out STD_LOGIC; Data_In : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); LRCLK : Out STD_LOGIC; DOUT : out STD_LOGIC; Reset : in STD_LOGIC; Empty : out STD_LOGIC ); end entity; architecture I2S_Transmitter_Arch of I2S_Transmitter is signal InputBuffer : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); signal Empty_Signal : std_logic := '1'; signal DOUT_D1 : std_logic := '0'; signal WS : std_logic := '0'; signal Counter : integer := 0; begin LRCLK_Logic: process (Clock) begin if(falling_edge(Clock)) then if(Reset = '1') then Counter <= 0; WS <= '1'; else Counter <= Counter + 1; if(Counter > (DATA_WIDTH / 2 - 1)) then WS <= '1'; else WS <= '0'; end if; if(Counter = (DATA_WIDTH - 1)) then Counter <= 0; end if; end if; end if; end process; Load_and_shift_out_Data: process(Clock) begin if(falling_edge(Clock)) then if(Reset = '1') then InputBuffer <= (others => '0'); Empty_Signal <= '1'; else if(Empty_Signal = '1') then InputBuffer <= Data_In; Empty_Signal <= '0'; else InputBuffer <= InputBuffer((DATA_WIDTH - 2) downto 0) & '0'; DOUT_D1 <= InputBuffer(DATA_WIDTH - 1); end if; if(Counter = (DATA_WIDTH - 1)) then Empty_Signal <= '1'; end if; end if; end if; end process; MCLK <= Clock; LRCLK <= WS; DOUT <= DOUT_D1; Empty <= Empty_Signal; end architecture I2S_Transmitter_Arch; With this Testbench: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity I2S_Transmitter_TB is -- Port ( ); end I2S_Transmitter_TB; architecture I2S_Transmitter_TB_Arch of I2S_Transmitter_TB is signal MCLK : std_logic; signal WS : std_logic := '0'; signal SCK : std_logic := '1'; signal DOUT : std_logic; signal Empty : std_logic := '0'; signal Reset : std_logic := '0'; signal Data_In : std_logic_vector(31 downto 0) := (others => '0'); -- 8,192 MHz Clock constant clk_period: Time := 122 ns; constant ws_period: Time := 16 * clk_period; begin DUT: entity work.i2s_transmitter port map ( LRCLK => WS, MCLK => MCLK, Data_In => Data_In, Clock => SCK, DOUT => DOUT, Empty => Empty, Reset => Reset ); CLOCK: process begin wait for clk_period / 2; SCK <= not SCK; end process; STIMULUS: process begin Data_In <= x"507B507B"; Reset <= '1'; wait for 10 us; Reset <= '0'; wait for 10 us; Data_In <= (others => '0'); wait for 30 ms; Reset <= '1'; wait for 5 ms; end process; end I2S_Transmitter_TB_Arch; I use Port JC on my ZYBO and this is my XDC-File: # Clock set_property PACKAGE_PIN L16 [get_ports Clock_In] set_property IOSTANDARD LVCMOS33 [get_ports Clock_In] set_property PACKAGE_PIN V15 [get_ports MCLK] set_property IOSTANDARD LVCMOS33 [get_ports MCLK] set_property PACKAGE_PIN W15 [get_ports LRCLK] set_property IOSTANDARD LVCMOS33 [get_ports LRCLK] set_property PACKAGE_PIN T10 [get_ports DOUT] set_property IOSTANDARD LVCMOS33 [get_ports DOUT] set_property IOSTANDARD LVCMOS33 [get_ports DEM] set_property PACKAGE_PIN T11 [get_ports DEM] The clock frequency for MCLK is 8,192MHz, generated with a MMCM. I´ve connected this speaker ( to the PMOD, but I doesn´t hear any sound. Why? Thank you for help!
  12. BitsAndBugs

    PMODI2S - No sound output!

    I trying to use the PmodI2S for the first time, but am unable to get sound from the port. I read thru the post "Pmodi2s Stereo Output Pmod - How Can I Get This Thing To Work?", but unfortunately it didn't solve my issue. I'm sending I2S audio to the pmodI2S module with a PIC32. The PIC32 is toggling the MCLK pin at 8.3 MHz (I've also tried 11 MHz). Here are the frequencies on the pins, verified with a scope: - MCLK (pin 1): 8.3 MHz (Supplied by PIC32) - LRCK (pin 2): ~31.45 kHz (2x channels) - SCK (pin 3): 2 MHz (I've tried it with the PIC32 supplying this and without supplying it, i.e. internal. When relying on internal, it outputs nothing.) - SDIN (pin 4): 16-bit data, 32-bits per channel (2x channels) = 64-bit frames - GND (pin 5): GND - VCC (pin 6): 3.3v I'm using Apple headphones that came with my phone to connect to the output jack. Been fighting this one for many several hours. Any help will the greatly appreciated. Thanks
  13. JGRMSL

    I2S L1

    I am working on a DIY project and I accidently used a heat gun to unsolder L1 on my PMOD I2C board I looked at the schematic but do not understand what the L1 part is with the 2500 designation. Some sort of choke filter? I was wondering if anyone could point me in the right direction on replacing this part. Thanks!!!
  14. attila

    I2s Interpreter

    I got this question from a customer: I have been playing with the raspberry pi and its I2S sound output I have noted the I2C interpreter, but to support I2S you need as second clock signal the LRCLK. This splits the data channel between the left and right information, at the moment using the SPI I can only see one channel based on the “select” input. Do you have any plans to update the software and maybe add I2S support? Is there a way to add I2S functionality via a third party API into the DWF software? Is there a 64 bit version on the way?