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Found 16 results

  1. Hi, I am a hardware designer tasked with coming up with HS2 compatible DLL's to suit a vendor requirement. We have a single tap JTAG for our project and have procured dozens of HS2 cables. Can you please point me to code snippets that could do the following, 1. INT32 openc(const char * ipaddress, const char * port) 2. INT32 readmem(UINT32 memAddress, INT32* valptr) 3. INT32 writemem(UINT32 memAddress, UINT32 val) 4. void closec() I looked into sample code in digilent.adept.sdk_v2.4.2\samples\djtg\DjtgDemo\DjtgDemo.cpp, but it is not clear to me how I could translate it to the commands that I would need. Thank you. ARP
  2. Hello , I am working with Metaware IDE and the device uses Digilent HS2 JTAG cable. But there is a problem with the JTAG cable and I could not identify the issue. Kindly guide me with this. I have attached the picture of the error. Thanks
  3. Hi, I use a HS2 cable with my Artix7 FPGA. Suddently, my HS2 cable became very hot (around the PCB), and now i can't program the FPGA anymore. HS2 is recognized with Vivado but FPGA part isn't recognize. Any idea? Something to do? Thanks
  4. Theo

    Damaged HS2 cable?

    I wonder if I have encountered the same issue as Mojy with my Digilent HS2 JTAG cable. I raise the question again because it looks like the question was answered, but by a private communication. I'm running Red Had Linux 7.4. I've installed the Adept Runtime and Utilities packages. Previously, running djtgcfg enum had listed the HS2 device. Now, it does not. However, the lsusb utility recognizes the device as Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC I see that this is the bridge chip inside the HS2. I think Mojy's original assessment of lost EEPROM may be correct. Can you help? Thanks, Theo
  5. While trying to configure a FT232H chip for my FPGA project through FT_prog, I mistakenly changed the configuration of the HS2 programming cable FT232H chip instead... The programming cable is no longer being detected by Vivado. Would anyone know where I could find these configurations or how I could reset them? Thank you Edit: Seems like others have had this issue before Would anyone be able to provide me with this configuration software?
  6. gm_

    JTAG HS2 completely silent

    Hi all, I have just tried my JTAG HS2 on 4 PC with windows and linux, but the device is not recognized by any of them. I also tried to change the usb cable to no avail. Any idea to what else I could do before sending it back? Thanks!
  7. OS: Window 10. My HS2 jtag cable is recognized by the device manager as "Digilent USB Device" but it is no longer found by the adept (2.4.2) utility. This is a cable that previously worked fine. I have disabled and reenabled it, reinstalled drivers. No change. Any help would be appreciated. thanks.
  8. Dear all, I would like to buy JTAG HS2, but I have the followings doubts: 1. is it recognised by Fedora? 2. does it support debugging? 3. does it work with urJTAG? 4. is it compatible with openOCD? Thanks! gm
  9. I'm using the JTAG-HS2 programmer with Universal Scan boundary scan software from Ricreations. Is it possible to change the TCK output frequency? Tech support for Universal Scan says the clock frequency is fixed.
  10. Hi, I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies). I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.) One possible solution is to use this: on my motherboard and daisy chain JTAG lines as per Xilinx docs. QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds. Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below: So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention). QUESTION: Thoughts? Does this seem reasonable? I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work. Thanks, Aditya
  11. Has anybody used one of the USB over CAT5/6 extenders with a Digilent JTAG programming cable? Something like this: We're trying to program devices that are either in different rooms or across the room from the programming computer. The main concern is that USB may not be able to supply enough power for both adapters and the JTAG device. Thanks, Will
  12. Hi, I have a digilent hs2 programmer. whenever i open impact (ise 14.7) to program the FPGA, the programmer is identified by impact, and i can initialize the chain successfully, but after a while (~1 min) it automatically disconnects and disappears from cable setup menu and also from device manager list. I use windows 8.1 64-bit. Could you help me solve this issue? Thank you in advance.
  13. Hi, I use JTAG HS2 with Synopsys Metaware for ARC debugging. I can download the information successfully. However, the speed is very slow. The download speed is about 1KB/s. I checked the protocol with logic analyzer and found the root cause is that the gap between IR and DR is about 1ms. One DWORD takes IR-DR-IR-DR. Was the gap caused by HS2 HW, driver or software? Thanks!
  14. Hello All, I have attached serially 4 Kintex-7 FPGA to program them in Serial JTAG configuration , All configuration works with 3 FPGA when we get to the 4 FPGA does not functioning at all. I have replaced the HS2 with Xilinx Cable 2-3 and evry things is working. It looks for me the issue of the FAN out of TMS and TCK signal . Is this is nothing to do with FTDI chip on the HS2 programmer whcih is going to limits the number of the FPGAs in the chain ? Any body have tested HS2 with this configuration ? any has solution for this ? BR Abbas
  15. I got this question from a customer: I'd really like to buy a compact USB JTAG programming cable for configuring Xilinx XC95xx CPLDs, but I don't know which one. In the docs for the HS3 cable it is explicitely stated that programming XC95 is not possible. For HS1 or HS2 there are no lists of target devices. Can HS1 or HS2 be used to programm XC95xx XPLDs? Can anyone help with this?
  16. I got this question from a customer: I'd really like to buy a compact USB JTAG programming cable for configuring Xilinx XC95xx CPLDs, but I don't know which one. In the docs for the HS3 cable it is explicitely stated that programming XC95 is not possible. For HS1 or HS2 there are no lists of target devices. Can HS1 or HS2 be used to programm XC95xx XPLDs? Can anyone help with this?