Search the Community

Showing results for tags 'hls'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 11 results

  1. Hello, my friends, i am new here and it is my first project. This project will be my BSC. I have to make next: 1. Make USB CAM interfacing on System Level using systemC... My diagrams are shown in the post. I need to capture the photo using a USB CAM. After that, the picture needs to be stored in some memory. After that the image processing logic (In my case, the logic needs to have the photo (stored in memory) as its input, the idea is just to decrease the photo size (pixels) and the output is the result (decreased size picture)), after that the result of processing needs t
  2. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negati
  3. PhDev

    Vivado HLS

    Hi, Do you have any experience of using Vivado High Level Synthesis, HLS? Today I use VHDL and C/C++ in microblaze. I am interested in testing HLS but don't know if it is worth spending time on that. Is it easy to get things running using HLS? What are the main pro/cons using HLS instead of VHDL/Verilog? Are the tools mature? Best regards
  4. the error are : note: candidate function template not viable: requires 3 arguments, but 5 were provided void dut_mmult_accel_core ( sorce/main.cpp:645:2: error: no matching function for call to 'dut_mmult_accel_core' dut_mmult_accel_core <float, 60, 1*60, 4, 5, 5>(in_stream, out_stream, predict_label1_hw_trig,precision1_hw_trig,prob_estimates_t1_hw_trig); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ `dut_mmult_accel_core <float, 60, 1*60, 4, 5, 5>(in_stream, out_stream, predict_label1_hw_trig,precision1_hw_trig,prob_estimates_t1_hw_trig)
  5. Hello, I have a Arty-Z7-20 board and got the hdmi_in demo working on it. I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required. I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS - #include <hls_video.h> void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out) { #pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM #pragma HLS INTERFACE a
  6. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h>
  7. HI there, I have a zed board. Developing a design in HLS for algorithmic acceleration. When I run the c-simulation for my design in HLS , it is not run showing the following error: But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?' why this happens and how do i understand this behavior? How can i get it corrected? Thaks in advance
  8. Hello there, This time i have a very simple design in HLS which takes in a 3d matrix, multiplies with a constant and gives output. It works for [64][64][64] matrix perfectly, but not for [128][128][128] matrix. Again I get the segmentation fault. Can somebody help me to know what fundamentally going wrong.. Thanks for your halp in advance. i have attached my design files here: core.cpp core.h core_test.cpp
  9. Hi experts, If i use trigonometric(sin or cos) or math functions (pow, floor, ceil ) in HLS with fixed point design it gives me error: what is the workaround? Thanks in advance. mlem_csim.log gravity_csim.log
  10. Hi there, I get this error when I run the C simulation in HLS to implement on zed board. I know that this error occurs when classes or class member functions are set as the top-level for synthesis. But i am not able to figure out where exactly i am going wrong. Can someone guide me here.?
  11. Hi every one, I want to a IP CORE for face detection that created by HLS. According to OpenCV function for face detection (Cascade Classifier), I found similar function in “hls/hls_video_haar.h” in to “hls_video.h” library, But I don’t know How can I use these function for face detection. Please help me about these topic. Best wishes.