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Found 5 results

  1. Hello, I am a college student currently working on the HDMI Input demo for the Zybo board on Vivado 2018.3 and SDK. I am following the steps provided on this forum, but I end up with trouble displaying the HDMI source onto the monitor. Without any modification, I can get the HDMI source to display properly; however, there seems to be many errors and warnings. In addition, modifying the C code by commenting out some of the switch statements resulted in no change whatsoever. After creating a new bsp and application project, followed by copy and pasting all of the source files, I had no errors popping up. I was able to see the results of the modifications I made, but the HDMI source wouldn't display onto the monitor (just the DemoPrintTest shows up). I have posted my project onto this link. https://drive.google.com/open?id=1lvM1tz8zgd_w3UtlYuTKOEKojWYyn3rg If possible, I would like to get help on this matter.
  2. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  3. zazou

    HDMI_IN Arty Z7-20 ERROR

    Bonjour, J'ai testé le code du projet HDMI_IN publié sur le GitHub d'ici sur la version 2016.4 de Vivado et j'ai eu cette erreur ! any Help !
  4. Hello, I have a Arty-Z7-20 board and got the hdmi_in demo working on it. I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required. I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS - #include <hls_video.h> void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out) { #pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM #pragma HLS INTERFACE axis port=video_out bundle=OUTPUT_STREAM hls::Mat<1080, 1920, HLS_8UC3> src; hls::Mat<1080, 1920, HLS_8UC3> dst; #pragma HLS dataflow hls::AXIvideo2Mat(video_in, src); hls::Scale(src, dst, 2.0, 0.0); //Simple processing hls::Mat2AXIvideo(dst, video_out); } My questions are - 1) Where in the demo block design should I connect this? (a) Between the video-to-axi4-stream ip and the axi-vdma ip (b) Add 1 more axi-vdma IP with both read and write channels and connect to it (c) Some better alternative? 2) In HLS, this design was synthesized with a clock constraint of 6.7 ns, so it meets the HDMI clock constraint of 148.5 MHz. However, in IP Integrator, a default value of 100 MHz is taken and I am unable to change this. What is the solution? 3) Is there any Digilent reference design/demo that already has HLS OpenCV IP integrated into the block design? Xilinx provides XAPP1167, but this only compiles on 2014.4 version which I don't have. I don't know how to upgrade the design to the current version. I might be asking too much, but any help is appreciated. Thanks, Rajat Rao
  5. https://reference.digilentinc.com/reference/software/sdsoc/reference-manual I am trying to run this design on zybo (hdmi_in project). I was able to have the baremetal design running on the board. But I am not sure how to have the linux version running as well. But there is no clear instructions on the link. Can some one help me get through the process? Thank you