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Found 51 results

  1. Hi Everyone, I was trying to capturing hdmi signal and display video on VGA monitor using DVI to RGB IP Core (version 1.6 or 1.7). Everything works correctly for 800x600 1024x768 and 1280x720. But for other resolutions (1280x1024 1600x900 1680x1050 and 1920x1080) image on external VGA monitor has very poor quality. Could anyone suggest where is the problem. In dvi2rgb spec I've found info about constraining tmds clock so based on my calculation for ZYBO IP Core should work correctly for 1680x1050 resoultion (tmds clock is about 120). I am using this IP Core in bigger project and I need to explain where is the problem. I can also upload my project in Vivado. Thanks for any help
  2. Hello everyone, I have been working in the arty z7, working to output HDMI video from a camera conencted by ethernet . While the ehternet hardware, driver and code are fully functional. I have yet to make the hdmi function on the OS. Currently, i have follow succesfully the following tutorial, that means that i have the hardware for HDMI in and out and can use through the provided Bare metal application. Now, i have to move this functional hardware form a bare metal application to a OS application, for that i need some drivers to control the Axi Stream conected to the VDMA and to the HDMI output. To be honest I dont even know where to start with this task, do any of you have any pointers, are there pre-developed drivers for this situation?. Thanks for any information PD: the current version of OS i am using is linaro, i dont think it changes anything but just in case.
  3. My noobish questions on Atlys HDMI demo

    Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! =) Question 1: I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Thank you very much for your help
  4. Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  5. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  6. Hi, I am new at this area. My current project required to know the use of HDMI and VGA port of Zybo board. As a starting point I got a sample demo project(https://github.com/Digilent/Zybo-hdmi-in) by digilent but that was done in Vivado 2016.4. I am working on Vivado 2017.2 windows PC. I successfully convert that project in current version and able to generate Bit stream successfully. The problem is when I lunch SDK, it gives me errors. Can anyone help me? Or can anyone gives me some simple project which from where I can get idea about how to use HDMI and VGA port? Thanks.
  7. [IP] dvi2rgb_v1_7 EDID compatibility

    Hi, I'm using the dvi2rgb/rgb2dvi cores (latest repository version) to make a simple passthrough in the FPGA and have huge issues with the EDID memory. Has it been confirmed at some point that the default 720p edid settings work properly with a GoPro Hero5 camera? I tried loading the default EDID, a properly cooperating monitor's EDID, prepared numerous EDIDs myself - every single one seems to fail so the camera is setting itself to the lowest supported resolution. Had a go with a Panasonic DMC-G3 camera too but it behaves the same way. Both sources work properly when connected directly to the monitor. The EDID values are being read properly, this has been verified on an oscilloscope (the camera seems to be reading the 128 edid bytes twice though).
  8. Problem with Arty7 HDMI demo

    I'm trying to run the HDMI-in and HDMI-out demos on my ARTY Z7 board and I'm having problems building the SDK side of the projects. The problems are the same for both of these projects. After importing the project in the SDK I get the following error: 09:07:45 ERROR : The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace. As a result, this BSP will not build properly. To fix this error, please import the associated hardware project or recreate a new BSP targeting an existing hardware platform. Upon building the project I get the following errors (sorry for the Polish): Description Resource Path Location Type ../config.make: No such file or directory hdmi_in_bsp line 38 C/C++ Problem config.make: No such file or directory hdmi_in_bsp line 33 C/C++ Problem fatal error: xil_types.h: No such file or directory video_capture.h /hdmi_in/src/video_capture line 74 C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/axivdma_v6_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/ddrps_v1_0/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/devcfg_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/dmaps_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/emacps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpio_v4_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpiops_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/iicps_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/qspips_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scugic_v3_5/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scutimer_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/sdps_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/standalone_v6_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/uartps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/usbps_v2_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/vtc_v7_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/xadcps_v2_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [src/video_capture/video_capture.o] Błąd 1 hdmi_in C/C++ Problem make[1]: *** [coresightps_dcc_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [profile_includes] Błąd 2 hdmi_in_bsp C/C++ Problem make[1]: *** [scugic_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scutimer_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scuwdt_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [standalone_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xadcps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xddrps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdevcfg_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdmaps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xemacps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xgpiops_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xiicps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xqspips_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xsdps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xuartps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xusbps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** Brak reguł do wykonania obiektu `config.make'. hdmi_in_bsp C/C++ Problem make[2]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[2]: *** Brak reguł do wykonania obiektu `../config.make'. hdmi_in_bsp C/C++ Problem While building the project in Vivado I had some other problems which I manged to solve. I described my build below. I have followed the instructions on Digilent's reference site for the project, that is: I'm using Vivado 2016.4, I've installed the board suport files, I've cloned the demos from the Digilent github repo along with the Vivado library IP-cores I've successfully generated the projects via the tcl script with one warning, which doesn't look critical: WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0/aRst_n(rst) Next I ran the Generate Bitstream option and got an error that the top module wasn't set. I've set the top module to hdmi_out and went through elaboration and synthesis where I got the following warnings: [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":82] [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":83] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":5] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc":11] [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Pfi 67-13] Hardware Handoff file hdmi_in_processing_system7_0_0.hwdef does not exist for instance processing_system7_0/inst Finally on bitstream generation I got the following error: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 6 out of 153 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDC_scl_i, DDC_scl_o, DDC_scl_t, DDC_sda_i, DDC_sda_o, DDC_sda_t. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. I've used the fix from https://www.xilinx.com/support/answers/56354.html to ignore these rules and managed to get a bitstream. Next, following the tutorial, I've exported the hardware along with the bitstream, but the export failed because no Hardware Handoff file was found. I followed the suggestions from https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Export-Hardware-Hardware-handoff-file-sysdef-does-not/td-p/539953 to manually generate the .sysdef file, and I managed to export the hardware and open the design in the SDK. I'm suspecting that the problem might be caused by the fact that I'm using Vivado installed by a different Windows user. I tried adding the Vivado and SDK location to the path variable, setting xilinx_sdk and xilinx_vivado variables, running the settings_64.bat scripts etc. but that didn't improve the outputs.
  9. Atlys + ISE 14.7 : HDMI demo problem

    Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a 640x480@60hz signal. The goal is to rotate it and output a 720p@60hz signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it would be a good start to understand how hdmi inputs and outputs work with the Atlys board : https://reference.digilentinc.com/_media/atlys/atlys/atlys_hdmi_plb_demo.zip To build the project, I'm using ISE 14.7, fresh install (Windows 7). Actually I can build the project and program the Atlys with it, and even run it. However it seems it doesn't work OK. I looks like there are problem with interrupts, especially with the push buttons on the board. Wichever button I push, the callback function is never called. However, I have evidence the program does run. If, for instance, I change the main function to make it draw thing on the screen, it does it. I can also print things in the virtual terminal of the SDK. For instance, if I do a xil_printf at the beginnig of main(), things print in the terminal. However If I put a xil_printf at the beginning of the button handler function, whichever button i press nothing prints ... reason why I think it might be an interrupt problem. Needless to say that Adept button test is OK. Other thing : I'm using a fresh ISE 14.7 out-of-the-box install. I don't know if specific add-ons need installing to make Atlys work flawlessly with EDK. I might have missed some things. Especially, on the Atlys Resource page on Digilent's website, there is a zip archive and the following comment : "Atlys board support files for EDK BSB wizard. Supports EDK 13.2 - 14.7 for both AXI and PLB buses." Do I need this ? I don't have a clue about what BSB wizard is... I think all has been said =) Thanks in advance to all helpers ! Cheers
  10. Hello everyone! I'm not sure whether this forum is the right place to ask this question but still. I have connected a low-cost OV7670 camera to this Digilent example: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start?redirect=1 Here is what I've done. I took the OV7670 - > AXI4Stream core from here (link below) and attached it instead of HDMI input. I changed this module to have not 32 bit RGBA output but 24 bit RGB input https://lauri.xn--vsandi-pxa.com/hdl/zynq/xilinx-video-capture.html and also I took the OV7670 Controller from here (link below) and also attached it to the design https://lauri.xn--vsandi-pxa.com/hdl/zynq/zybo-ov7670-to-vga.html The system works o'k. What I would like to do is to remove the HDMI part from this design. I just want the image to be captured by the camera and be shown on VGA screen. If I understand it right the axi_gpio_video and the v_tc_1 ip-cores send some interrupt essential for the stream to start. I am interested and I have no understanding of what I have to do to remove the HDMI part from the design so that I always saw the image from my OV7670. Do I have to somehow simulate the interrupts? Can I do this in C code? Thank you very much for response in advance.
  11. I recently upgraded from version 1.6 of the DVI to RGB IP to version 1.7. I'd used version 1.6 for a while and didn't have any issues, but after upgrading, I'm finding that I can't get my setup to work in conjunction with Xilinx's Video In to AXI4S and AXI4S to Video Out IP as part of a video processing pipeline while receiving 1080p video. Any resolutions < 1680x1050 work fine, but as soon as I go up to 1920x1080 I start getting single cycle underflow errors during the tlast blanking periods, as seen in the below waveform. These underflows don't occur every frame- occasionally I'll see (in the ILA window) a frame where there are no underflows, although they return on the next frame. Here's my block diagram: I'm driving one monitor and the Zybo from a Windows 7 PC via HDMI. The Zybo is connected to a second monitor via VGA. My PC is set to extend the displays. I've been using this setup for a few months now without issue, and didn't have any problems until upgrading the IP recently. I could go back to v1.6 of the IP, but I'd prefer not to as you had to manually move the EDID .txt files into your projects source folder every time you started a new run, which was a big hassle. Dvi2rgb settings are >= 120MHz, 1920x1080. The clock wizard is generating a 200MHz reference clock with a PLL. Video In to AXI4S and AXI4S to Video Out have 4096 element deep FIFOs. The timing controller generator is based off of the timing received at the detector. Everything meets timing. If I go directly from the dvi2rgb block to the rgb2vga block, it yields a working video stream at 1080p; however, to do any sort of processing, I need to convert to an AXI4 Stream. Has anyone else had an issue with this version of the DVI to RGB IP when used in conjunction with the Xilinx AXI4S Video blocks, or does anyone have an idea as to what could be causing this? Edit: I just found that changing my desktop background from something complex, like a mountain or city, to something like a solid color, or an image with a border around it works fine at 1080. If I have a complex background and I'm not seeing any output with a 1080p input, and I then drag a browser or Windows explorer window over to the second monitor, everything will lock on and begin working.
  12. HMDI to VGA on ZYBO demo 1080p problem

    Hi, I’ve followed the ZYBO HDMI Demo available from the Digilent website. The basic options worked fine, however when trying out 1080p I get an image that appears to be bouncing up and down a bit. This is very annoying and undesired. Vivado gives the following critical warining when running the implementation: [DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell hdmi_in_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator. The computed FVCO is 599.952 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 5.000, CLKIN1_PERIOD = 8.33400, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)). This violation may be corrected by: 1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range. 2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range. 3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range. 4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin. This only occurs when the TMDS clock range op the dvi2rgb IP core is changed from < 120 MHz to >= 120 MHz (1080p) and 1920x1080 selected as my preferred resolution. I also selected 1080p as the default video mode for the video timing controller that goes to the output. From this critical warning it appears to be a clocking error. I also checked out the DVI_ClkGenerator that is referenced in the warning, which explains that MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result in a correct VCO frequency for 1080p. Changing values in this component doesn’t seem to have any effect. CLKIN1_PERIOD is always 8.334, even when I change its value in the generic map. So, I’m wondering what I need to change to be able to display 1080p streams correctly? Thanks in advance.
  13. New user - problem finding documentation

    Hi, I'm new to FPGAs and I have trouble finding documentation. In particular: How exactly VSync and HSync is handled for HDMI input? What can I assume about them? I'd like to create a AXI Master to store input in DDR. However I cannot find a reference for AXI4M_bus_port - how is timing handled for write_burst? Are there any guaranteed on ordering of stores through AXI Master to DDR? Matt
  14. Hi, I am trying to develop a simple project for HDMI to RGB. I am using dvi2rgb core and clock_wizard for generating a reference clock for it. I supplied 200MHz to dvi2rgb. I tried both MMCM and PLL modes in clock_wizard configuration. But when I dump the bitstream on Zybo Vivado shows the following warnings and my design doesn't work. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution:1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. Attached are my block diagram which I'm implementing, and my constraints file. Please help me. I have read a lot of posts on this project but couldn't find any solution that can work for me. If you want my project file I can attach it as well. Thanks ZYBO_Master.xdc
  15. Displayport on Genesys2 again (OOB version 2 may)

    Hi guys Sorry if I'm back i compiled the OOB design downloaded from your site, the ZIP file (dated 2 may 2017),,,,, the result is that Displayport continuates to be correctly trained and configured, but screen does not display. Additionally, in this version HDMI does not work too. At this point I suspect a problem in RTL (BD, constraints) sources. May you check the functionality of your distribution on a Genesys2 Board? Thanks in advance. P.S. Obviousy with other designs HDMI works fine, and with project available in flash displayport too,
  16. I'm working on a simple HDMI capture and transmission to PC using DPTI. My HDMI decoder is modified code from @hamster and DPTI code is from Digilent Adept SDK package. I have tested both of them on their own but when I try implement them together I get the following error. When I add the sugested line to my constraints then I get this error. And adding this line gives me that when generating a bitstream. I have tried adding BUF elements to the HDMI design but then SerDes and TMDS decoder stop working.
  17. Hi there, I was attracted to Digilent from google searches and the Nexys Video Artix-7 FPGA caught my eye. I want to take an Apple TV hdmi output and overlay a countdown clock on it. The countdown would have to be adjustable somehow either through a wired or wireless connection. Do you know of a suitable product for me? The Nexys Artix-7 seems like it may be a lot bigger than what I need. Thanks so much! Sincerely, Garry
  18. Hello, I am trying to initialize the ADV7611 Chip of the Digilent FMC-HDMI add-on Board. But I can't find the needed addresses for it (this doesn't help). I am using the xiic.h Driver from xilinx. The initalization of ADV7511 Chip of the zc702 was successfully. Have anyone a idea?? I am using the zc702 and the digilent FMC-HDMI Card.
  19. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  20. Hi every one, I'm trying to have My Smartphone (Sony Xperia Z2) MHL (TV-OUT) output in ZYBO HDMI input. When I use my laptop HDMI output (720p), the ZYBO works correctly, But when I connect My Smartphone via MHL(Mobile High-Definition Link) cable, Idon't have any output from VGA port. I must say that I tested phone MHL output on TV and it worked perfectly (1280*720@60Hz & 1920*1080@30Hz). Please help me about this problem. Best regards. Sina shiri
  21. The dvi2rgb IP core seems to take anywhere from 5 seconds to 20 seconds to acquire synchronization and display incoming HDMI data. The datasheet says the process could take up to 1 minute. The pixel clock achieves lock quickly, it's just the data/syncs that takes some time to appear. I hate to complain, because the core is provided free of charge with the Nexys Video card, and seems to work quite well otherwise, but Is there any way to speed up the acquisition time, or perhaps in a future update?
  22. Problems with dvi2rgb at low resolutions

    I've got a HDMI link set up between two Zybos using Digilent's DVI cores (rgb2dvi and dvi2rgb). Having tested everything successfully using a 1080p pipeline, however upon switching to VGA resolutions (640x480) the sink part cannot successfully decode the stream. It never occurred to me that low resolutions would pose an issue - but I've been banging my head on a wall with this one! As per the documentation, I've adjusted some constraints and multiplier / divider combinations for the MMCM in the dvi2rgb core and the clock recovery block is successfully recovering my 25.175 MHz pixel clock (although interestingly it is somehow still able to recover it when the MMCM is configured for 1080p - something I wasn't expecting as the VCO is operating way out of spec at 125 MHz). I'm not getting any activity on the pVDE or CTRL signals, so I think there's something up with the phase alignment or channel bonding. Receiver block diagram is attached, but it's pretty standard. Any clues? EDIT: I've just noticed that the documentation lists the lower limit for the pixel clock as 40 MHz. Initially I thought this was due to the VCO range, but I also just noticed that the 32-tap delay spans 2.5ns, which happens to be the period of a single bit at 40 Hz. Is my limitation down to the deskew implementation?
  23. Zybo HDMI in example project

    I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me. Any help would be appreciated. This is the 3rd or 4th tutorial/example I have tried since getting the board today. All in all everything has gone smoothly up to this point, but I have not the fpga/vivado experience to determine the issue. also my log output from vivado is attached. implementation.txt
  24. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy
  25. Good afternoon, We use digilent boards in our curriculum at University of Delaware electrical engineering department. Next semester, we are upgrading our freshman digital design course from BASYS2 to ZYBO boards. Our enrollment is typically 150 students. We would like to add a project at the end of the semester that will be based on your HDMI example here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start The idea is to give the student introduction to HDMI and let them make changes to the code you provide to do something cool with incoming video. We have a group of students who are trying to do this as an exercise right before the class starts next semester. They have run into trouble - they can't change the VHDL code that is generated by your example. The code generated is marked "read only". Even when they make changes outside of VIVADO, the system overwrites their changes. My question to you is - can you share with us a method which can be used to add lines of code to your code examples. Please let us know ASAP, Fouad Kiamilev Professor ECE Department UDEL