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Found 63 results

  1. Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA (1280x1024@60fps). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.
  2. HDMI doesn't seem to work - no signal

    I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  3. Adding custom IP in Zybo HDMI demo project

    Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  4. Error customizing/repackaging dvi2rgb IP

    Good morning, I am currently working on a project that uses the DVI2RGB IP on a custom-built PCB like the zybo-z7 board (but uses the zynq 7020 like the zed board) and would like to make my own version of the IP for several reasons but have encountered the following errors: 1) My PCB board has 2 HDMI ports configurable as sink/source, however when using 2 instances of the DVI2RGB core I get the following error: (error1.png) 2) I would like to make a generic data protocol around the HDMI connector that doesn't require blanking and the DVI2RGB core is a nice, open-source platform for me to experiment with new configurations. However, when repackaging the IP regardless of whether I make any changes I get the following error: (error2.png) For 1) I know I can solve my problem by modifying the IP (and probably just by adding a top-level constraint file to overwrite the dvi2rgb.xdc file), but because of the error in 2) I cannot accomplish this task. I have searched these forums as well as Xilinx with no luck regarding this problem. I have also searched through the Xilinx documentation (UG1118) on IP packaging, but was unable to find any useful information about something I may be doing wrong. I have also tried modifying the IP every way I can think of to remove the dependency on the board.xit file, but with no luck. If anyone has tried this or encountered similar problems with modifying any Diligent IP your advice would be greatly appreciated! Just to reiterate, I only really care about being able to repackage the dvi2rgb core myself, and the error above appears simply from editing the IP in the IP packager, leaving everything set as its default and repacking it. The first time I open the IP there is no implementation file group and the file utils/board/board.xit doesn’t exist, but when I repack it I get the error and when I reopen it in the ip packager again the file is there: (ippackager.png) Some info on my setup: I am running windows 10 64 bit, using vivado 2017.1 and have tried this with both dvi2rgb 1.6 and 1.9. If any additional information is needed please let me know. In the upcoming semester I will be helping mentor a group of undergraduate students on the contents of this IP, so resolving this before the semester starts would be a huge help. Best regards, Tyler Browning
  5. dedicated HDMI ports on the Zybo Z7

    hello, The Zybo Z7 has 2 HDMI ports, RX and TX. On the Zybo you had one port which could serve as input or output. Since the PHY is still implemented in the FPGA I wonder what the advantages are with this change, because before you could have set the ports as input or output as you like.
  6. No Output with Arty Z7 HDMI Demo

    Hi all, I started playing around with an Arty Z7 board and downloaded the hdmi out demo. As a first test, I used the bitfile from the SDK and loaded into the FPGA with the Xilinx SDK 2017.3. I guess with the provided bitfile, SDK version does not matter... JTAG jumper set. FPGA configured successfully I used the SDK terminal to connect to serial port but still do not get any output like depicted in https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start Also I do not get any signal on my display through HDMI cable. What am I doing wrong? Thank you very much in advance!
  7. Hello! I cannot debug the DDR3 outputs/inputs. I get the following error message. Bus interface connection '/mig_7series_0_DDR3' is connected to interface '/mig_7series_0/DDR3' with VLNV xilinx.com:interface:ddrx:1.0, which is not debug-able by System ILA IP. HDL attribute 'DEBUG' will not be set to this bus interface connection. Could anybody help me with this? I am going to check if my 640x480 picture is saved in the ddr3 but I have to use the ILA which does not work atm. regards, John
  8. nexys video HDMI Demo

    Hello, My FPGA board is nexys video,vivado is 2016.4, I Download and Launch the Nexys Video HDMI Demo,It have an error when generating a bit file,How to solve it? thanks Ali
  9. XAPP 495 fixed on digilent atlys spartan 6

    Hi, I was trying to get a single input from J3 to show on HDMI out J2 using xapp495 fixed on which can be downloaded as: https://joelw.id.au/FPGA/DigilentAtlysResources The problem that I am getting is that my output monitor says that it is NOT OPTIMUM MODE. RECOMMENDED MODE IS 1920x1080. The configuration of the jumper wires is shown in the figure below. I tried all button configurations but didnt see a single frame. I tried to implement VTC_DEMO seperately and I was able to see some coloured pattern generated on the monitor but if I implement DVI_demo/...... It took a lot out of me but didnt give me anything....... Serious help required from the professional engineers out there. thank you
  10. Hello! I get the following error when I am going to run the createproject.tcl. Do I have to download an earlier version than 2017.3, if so is there a way to not do it since it takes me a lot of time to (uninstall and install) different versions. The error is: [Board 49-71] The board_part definition was not found for digilentinc.com:nexys_video:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a200tsbg484-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store. The reason why I want to run this project is simply because to see if the MIG7 IP is used without a uB which is what I am seeking for. regards, John
  11. HDMI in and out of Digilent atlys Spartan 6

    I downloaded the HDMI demo from the given link https://reference.digilentinc.com/atlys:atlys:atlys I had XPS 14.7 while this project was made in 14.3, I was able to export the design and launch the SDK and import the hardware profile but I couldn't create a C project with all given files copied from the given link, It was step No. 4 in the given document. But exporting the SDK gave me a .bit file and instead of programming it through SDK, I programmed FPGA through ADEPT using the generated .bit file from the project. But the result that I got was as shown in the given figure, I got three patches with nothing going on. I request everyone with sufficient knowledge to guide me as this is my FYP and I need extreme guidance.... Thank you
  12. Live video processing on Zybo board?

    Dear expertise, I have implemented the hybo_hdmi_in demo and it's perfectly working. Now, I want to show a binary mask in the region of interest at the VGA output. Now, my question, Is it possible to do it only by modifying video_demo.c file. Any kind of coding related idea will be helpful. Thanks in advance- Shuvo
  13. Nexys Video HDMI Capabilities

    Hello, I'm trying to understand the HDMI capabilities of the Nexys Video Artix-7. I don't own a board yet, so these queries are based on reading spec sheets; please excuse any errors or omissions on my part. The FPGA on the Nexys Video is XC7A200T-1SBG484C, which supports 4 GTP transceivers at 3.75 Gbit/s [1]. However, based on my best interpretation of the Nexys Video data sheet [2] the HDMI ports aren't using the GTP transceivers. The GTPs are used for DisplayPort and FMC connector. Given the HDMI ports aren't using the GTPs, what is the maximum data rate the FPGA can support for them? The HDMI input has an Analog AD8195 buffer, which supports 2.25 Gbps data rate [3]. The HDMI output has a TI TMDS141 buffer, which also supports a 2.25 Gbps data rate [4]. This seems to limit the Nexys to 720p60 or 1080p30, whatever the FPGA may be capable of. Though if these rates are per TDMS channel then that's plenty for 1080p60. However, in the Digilent HDMI demo a video format of 1080p60 is shown [5]. In summary, can someone clarify what video formats and data rates the Nexys Video is capable of on HDMI input and output? Thanks in advance, Will For reference the data rate of some common HDMI formats: 720p60 - 1.45 Gbit/s (HDMI 1.0+) 1080p30 - 1.58 Gbit/s (HDMI 1.0+) 1080p60 - 3.20 Gbit/s (HDMI 1.0+) 2160p30 - 6.18 Gbit/s (HDMI 1.4+) 2160p60 - 12.54 Gbit/s (HDMI 2.0+) [1] https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf (page 50) [2] https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexysvideo_rm.pdf [3] http://www.analog.com/en/products/audio-video/hdmidvi-transmitters/ad8195.html [4] http://www.ti.com/product/tmds141 [5] https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-hdmi-demo/start
  14. Image Processing on Zybo

    I'm making a project about image processing. The board used in the project is the Zybo board and operates on a frame 1920x1080 (Full HD). My project is Square Area Detection Then motion detection within the rectangular area. I would like to ask for advice or guidance directs the operation of the mine. (I'm new to Zybo boards and I just learned recently.) If anyone has suggestions and links for learning. Please direct me and attach the link. Thanks in advance. ^__^
  15. I'm working with the HDMI ports on a Zybo Z7-10 development board, and I'm trying to set it up as an HDMI passthrough. As in, the HDMI input signal would simply be fed into the HDMI output port without any processing in between. I will eventually be filtering the video signal but I'm using this passthrough as a starting point. The HDMI hardware on my Zybo, as well as my HDMI source and output screen, are all confirmed working because I've been able to run Digilent's HDMI demo on it. I'm using Vivado 2017.3 I was able to get my block design started by following this forum post, replacing the VGA output with an HDMI output. I can currently feed my input video signal to my HDMI output. However, my output video quality looks horrible. I'm currently using a laptop as my HDMI source, and a custom built screen as my video output. This album shows pictures of my video output. The output of the color gradient contains a lot of vertical lines, and the color transitions are not smooth. The color bar also contains the same vertical lines, although not as visible. For the most part the colors on the output screen match the colors of the original image. I've also tried displaying a vertical color gradient, and same vertical lines appear, as well as a bunch of horizontal lines. Attached is a picture of my current block diagram. The DDC pins are connected to scl and sdi of the hdmi rx port. The output of the clocking wizard is 200MHz. GND and VDD are constant blocks of value 0 and 1 respectively. The system clock is configured as follows: set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; I suspect it might be a clocking issue, but I'm not sure which clock signal to alter, and what frequency to set it to. Let me know if I can provide any additional information.
  16. Video output at VGA monitor

    Dear experts, I am actually new in this field and have a very few experience with zybo board. I have implemented the zybo_hdmi_in_demo which is required for my master thesis. Output video streaming at the VGA monitor shows a cropped part of my input video source. What should I do now? And can I use other HDMI source rather than my PC? And what is the preferred input HDMI video resolution? any kind of support or suggestions is highly appreciated.
  17. Hi Everyone, I was trying to capturing hdmi signal and display video on VGA monitor using DVI to RGB IP Core (version 1.6 or 1.7). Everything works correctly for 800x600 1024x768 and 1280x720. But for other resolutions (1280x1024 1600x900 1680x1050 and 1920x1080) image on external VGA monitor has very poor quality. Could anyone suggest where is the problem. In dvi2rgb spec I've found info about constraining tmds clock so based on my calculation for ZYBO IP Core should work correctly for 1680x1050 resoultion (tmds clock is about 120). I am using this IP Core in bigger project and I need to explain where is the problem. I can also upload my project in Vivado. Thanks for any help
  18. Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  19. My noobish questions on Atlys HDMI demo

    Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! =) Question 1: I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Thank you very much for your help
  20. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  21. Hi, I am new at this area. My current project required to know the use of HDMI and VGA port of Zybo board. As a starting point I got a sample demo project(https://github.com/Digilent/Zybo-hdmi-in) by digilent but that was done in Vivado 2016.4. I am working on Vivado 2017.2 windows PC. I successfully convert that project in current version and able to generate Bit stream successfully. The problem is when I lunch SDK, it gives me errors. Can anyone help me? Or can anyone gives me some simple project which from where I can get idea about how to use HDMI and VGA port? Thanks.
  22. [IP] dvi2rgb_v1_7 EDID compatibility

    Hi, I'm using the dvi2rgb/rgb2dvi cores (latest repository version) to make a simple passthrough in the FPGA and have huge issues with the EDID memory. Has it been confirmed at some point that the default 720p edid settings work properly with a GoPro Hero5 camera? I tried loading the default EDID, a properly cooperating monitor's EDID, prepared numerous EDIDs myself - every single one seems to fail so the camera is setting itself to the lowest supported resolution. Had a go with a Panasonic DMC-G3 camera too but it behaves the same way. Both sources work properly when connected directly to the monitor. The EDID values are being read properly, this has been verified on an oscilloscope (the camera seems to be reading the 128 edid bytes twice though).
  23. Atlys + ISE 14.7 : HDMI demo problem

    Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a 640x480@60hz signal. The goal is to rotate it and output a 720p@60hz signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it would be a good start to understand how hdmi inputs and outputs work with the Atlys board : https://reference.digilentinc.com/_media/atlys/atlys/atlys_hdmi_plb_demo.zip To build the project, I'm using ISE 14.7, fresh install (Windows 7). Actually I can build the project and program the Atlys with it, and even run it. However it seems it doesn't work OK. I looks like there are problem with interrupts, especially with the push buttons on the board. Wichever button I push, the callback function is never called. However, I have evidence the program does run. If, for instance, I change the main function to make it draw thing on the screen, it does it. I can also print things in the virtual terminal of the SDK. For instance, if I do a xil_printf at the beginnig of main(), things print in the terminal. However If I put a xil_printf at the beginning of the button handler function, whichever button i press nothing prints ... reason why I think it might be an interrupt problem. Needless to say that Adept button test is OK. Other thing : I'm using a fresh ISE 14.7 out-of-the-box install. I don't know if specific add-ons need installing to make Atlys work flawlessly with EDK. I might have missed some things. Especially, on the Atlys Resource page on Digilent's website, there is a zip archive and the following comment : "Atlys board support files for EDK BSB wizard. Supports EDK 13.2 - 14.7 for both AXI and PLB buses." Do I need this ? I don't have a clue about what BSB wizard is... I think all has been said =) Thanks in advance to all helpers ! Cheers
  24. Problem with Arty7 HDMI demo

    I'm trying to run the HDMI-in and HDMI-out demos on my ARTY Z7 board and I'm having problems building the SDK side of the projects. The problems are the same for both of these projects. After importing the project in the SDK I get the following error: 09:07:45 ERROR : The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace. As a result, this BSP will not build properly. To fix this error, please import the associated hardware project or recreate a new BSP targeting an existing hardware platform. Upon building the project I get the following errors (sorry for the Polish): Description Resource Path Location Type ../config.make: No such file or directory hdmi_in_bsp line 38 C/C++ Problem config.make: No such file or directory hdmi_in_bsp line 33 C/C++ Problem fatal error: xil_types.h: No such file or directory video_capture.h /hdmi_in/src/video_capture line 74 C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/axivdma_v6_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/coresightps_dcc_v1_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/ddrps_v1_0/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/devcfg_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/dmaps_v2_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/emacps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpio_v4_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/gpiops_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/iicps_v3_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/qspips_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scugic_v3_5/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scutimer_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/sdps_v3_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/standalone_v6_1/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/uartps_v3_3/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/usbps_v2_4/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/vtc_v7_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [ps7_cortexa9_0/libsrc/xadcps_v2_2/src/make.include] Błąd 2 hdmi_in_bsp C/C++ Problem make: *** [src/video_capture/video_capture.o] Błąd 1 hdmi_in C/C++ Problem make[1]: *** [coresightps_dcc_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [profile_includes] Błąd 2 hdmi_in_bsp C/C++ Problem make[1]: *** [scugic_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scutimer_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [scuwdt_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [standalone_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xadcps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xddrps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdevcfg_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xdmaps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xemacps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xgpiops_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xiicps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xqspips_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xsdps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xuartps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** [xusbps_includes] Błąd 1 hdmi_in_bsp C/C++ Problem make[1]: *** Brak reguł do wykonania obiektu `config.make'. hdmi_in_bsp C/C++ Problem make[2]: *** [include] Błąd 1 hdmi_in_bsp C/C++ Problem make[2]: *** Brak reguł do wykonania obiektu `../config.make'. hdmi_in_bsp C/C++ Problem While building the project in Vivado I had some other problems which I manged to solve. I described my build below. I have followed the instructions on Digilent's reference site for the project, that is: I'm using Vivado 2016.4, I've installed the board suport files, I've cloned the demos from the Digilent github repo along with the Vivado library IP-cores I've successfully generated the projects via the tcl script with one warning, which doesn't look critical: WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_dynclk_0/LOCKED_O(undef) and /rgb2dvi_0/aRst_n(rst) Next I ran the Generate Bitstream option and got an error that the top module wasn't set. I've set the top module to hdmi_out and went through elaboration and synthesis where I got the following warnings: [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":82] [Common 17-55] 'set_property' expects at least one object. ["C:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/constraints/ArtyZ7_7020Master.xdc":83] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":5] [Common 17-55] 'get_property' expects at least one object. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/hdmi_in_v_vid_in_axi4s_0_0_clocks.xdc":11] [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. ["c:/Users/p1814/Documents/Arty-Z7-demos/Arty-Z7-20-hdmi-in/src/bd/hdmi_in/ip/hdmi_in_v_tc_1_0/hdmi_in_v_tc_1_0_clocks.xdc":6] [Pfi 67-13] Hardware Handoff file hdmi_in_processing_system7_0_0.hwdef does not exist for instance processing_system7_0/inst Finally on bitstream generation I got the following error: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 6 out of 153 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDC_scl_i, DDC_scl_o, DDC_scl_t, DDC_sda_i, DDC_sda_o, DDC_sda_t. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. I've used the fix from https://www.xilinx.com/support/answers/56354.html to ignore these rules and managed to get a bitstream. Next, following the tutorial, I've exported the hardware along with the bitstream, but the export failed because no Hardware Handoff file was found. I followed the suggestions from https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Export-Hardware-Hardware-handoff-file-sysdef-does-not/td-p/539953 to manually generate the .sysdef file, and I managed to export the hardware and open the design in the SDK. I'm suspecting that the problem might be caused by the fact that I'm using Vivado installed by a different Windows user. I tried adding the Vivado and SDK location to the path variable, setting xilinx_sdk and xilinx_vivado variables, running the settings_64.bat scripts etc. but that didn't improve the outputs.
  25. Hello everyone, I have been working in the arty z7, working to output HDMI video from a camera conencted by ethernet . While the ehternet hardware, driver and code are fully functional. I have yet to make the hdmi function on the OS. Currently, i have follow succesfully the following tutorial, that means that i have the hardware for HDMI in and out and can use through the provided Bare metal application. Now, i have to move this functional hardware form a bare metal application to a OS application, for that i need some drivers to control the Axi Stream conected to the VDMA and to the HDMI output. To be honest I dont even know where to start with this task, do any of you have any pointers, are there pre-developed drivers for this situation?. Thanks for any information PD: the current version of OS i am using is linaro, i dont think it changes anything but just in case.