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Found 80 results

  1. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?
  2. i want to work on a video project which board will be better zybo or pynq . as i have studied that pynq has unbufferd hdmi. suggestions will be highly appreciated. Thanks
  3. blacklight

    What is the best solution? for HDMI projects.

    I'm starting in the FPGA world and would like to know what the best digilent FPGA solution for HDMI projects. What I intend to do is a split monitor. Where two incoming HDMI signals are displayed on a single monitor. Arty A7: Artix-7 FPGA Development Board for Makers and Hobbyists is it enough for this project? thanks
  4. Aniq

    integrating python and verilog

    can we use output from python code in verilog on pynq board. e.g if we take hdmi in python. Can we process that frames in verilog.? Thanks
  5. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used the diligent dvi2rgb and rgb2dvi IPs. Have used a PLL (not MMCM) to generate the ref_clk (125MHz is board input and the PLL produces the 200MHz clk required delay taps). I have attached my top level VHDL file which shows the connections. I have also attached the XDC file. Note that in the XDC I have changed the tmds_rx_clk frequency to 80MHz which is suitable for a HDMI data source with 720p resolution (else there will be Impl errors as the Z7-10 has a -1 speed grade FPGA). Bit stream was successfully generated without timing errors. The synth design is as shown below. The design is not working after I have downloaded the bitstream. So the most important question is if the above makes sense? If the above is rubbish, then what can I do to improve my design? I just want to pass HDMI data from Rx port to the Tx port. Do I need to do some buffering of the pixel data (3 FIFOs for each channel with 8bits width, depth - I don't know ) before connecting vid_pData from dvi2rgb to rgb2dvi? Else what would help? Any help/suggestions are appreciated. Regards. hdmi_pass_top.vhd hdmi_pass.xdc
  6. cgarry

    HDMI In to VGA out on Zybo

    I'm trying create a PL subsystem that takes a HDMI video in and outputs it on the VGA. I got the digilent IP from this github https://github.com/Digilent/ZYBO.git and I created a HDMI in to VGA out loop in Vivado as shown below I have set the clock wizard up to provide 200MHz to the dvi2rgb block and the clock wizard block has an input clock 125MHz. I programmed the dvi2rgb block with the following config After trying to generate the bitstream for this I'm getting critical errors at the implementation stage saying it can't meet timing. It managed to generate the bitstream but its output an video from the VGA. Any ideas what is causing these timing errors? or where I am going wrong with the implementation? ZYBO_Master.xdc.txt
  7. Hello, New to this forum and my first post. I want to run the HDMI demo by following this: https://github.com/Digilent/Zybo-Z7-10-hdmi However this is for Vivado 2016.4 . Now I want to modify the TCL script so that I can run this DEMO using Viv2017.4. I have run into problems while trying to run it directly (if needed I post the error details). 1. Does a migrated project already exists? 2. If <1> is false, then how can I migrate the TCL script? Any guidelines, references? Thanks.
  8. Hello,

    how to use the FMC (in zynq7000 zedboard) as A/D converter?

  9. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  10. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: http://www.elpcctv.com/mi5100-5mp-usb-camera-module-usb20-aptina-125inch-color-cmos-sensor-100degree-lens-p-221.html CSI-2 Camera: https://www.waveshare.com/product/rpi-camera-f.htm DLP 2000 RGB - projector: http://www.ti.com/tool/DLPDLCR2000EVM HDMI projector: https://www.ebay.in/itm/302673956725?aff_source=Sok-Goog Display : https://www.alibaba.com/product-detail/5-inch-720p-oled-display-720_1925219941.html?spm=a2700.7724838.2017115.42.6ba11d77AqfGq7 Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  11. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  12. chcollin

    AXI4 HDMI demo for Atlys

    Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
  13. Hello, I am trying to initialize the ADV7611 Chip of the Digilent FMC-HDMI add-on Board. But I can't find the needed addresses for it (this doesn't help). I am using the xiic.h Driver from xilinx. The initalization of ADV7511 Chip of the zc702 was successfully. Have anyone a idea?? I am using the zc702 and the digilent FMC-HDMI Card.
  14. Mohammad Ahmad

    FMC-HDMI

    FMC-HDMI can work at 1080p@30fps/24bit RGB and 720p@60fps/24bit RGB (HDTV)?
  15. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  16. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  17. dgottesm

    YCbCr 4:2:2 in HDMI- Zybo Z7-20

    Hi all Here is a quote from Wikipedia's page on HDMI "HDMI permits sRGB 4:4:4 chroma subsampling (8–16 bits per component), xvYCC 4:4:4 chroma subsampling (8–16 bits per component), YCbCr 4:4:4 chroma subsampling (8–16 bits per component), or YCbCr 4:2:2 chroma subsampling (8–12 bits per component). The color spaces that can be used by HDMI are ITU-R BT.601, ITU-R BT.709-5 and IEC 61966-2-4." I have a video in 8 bit 480p YCbCr 4:2:2 format sitting in BRAM, and I want to output it with HDMI. I have a Zybo Z7-20 board. Is there a way to output the data directly without converting to other color spaces. If I do have to convert, than can someone explain the process that needs to be done, both in theory and in practice? This person seems to think that HDMI is simple enough: http://www.fpga4fun.com/HDMI.html, but he has 4:4:4 RGB. EDIT: I thought about it a little more...It could be that switching to another color space is not 'my problem'. It could be the receiver's responsibility. Meaning that the HDMI screen has to be told to be prepared to receive YCbCr 4:2:2... If this is the case, in what format do I send my data to the HDMI port...what does it expect... HDMI has three differential data lines, a clock, VCC and ground, (the rest I can ignore) so I assume it gets serial data... Anyone with any ideas, anything to add/fix... EDIT 2: Here is a quote from the HDMI protocol "Video data is carried as a series of 24-bit pixels on the three TMDS data channels. TMDS encoding converts the 8 bits per channel into the 10 bit DC-balanced, transition minimized sequence which is then transmitted serially across the pair at a rate of 10 bits per pixel clock period." I did not understand all of this, but I think it means that the data is sent at 8 times the rate as the clock... so maybe its not as simple as I thought... still welcoming words of advice...
  18. Shuvo Sarkar

    Zybo Grayscale output.

    Dear experts, I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? thanks- Shuvo
  19. Shuvo Sarkar

    Zybo hdmi in demo project resolution issues.

    Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start Regards- Shuvo
  20. Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA (1280x1024@60fps). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.
  21. Maciej Piechotka

    HDMI doesn't seem to work - no signal

    I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  22. tbrowning

    Error customizing/repackaging dvi2rgb IP

    Good morning, I am currently working on a project that uses the DVI2RGB IP on a custom-built PCB like the zybo-z7 board (but uses the zynq 7020 like the zed board) and would like to make my own version of the IP for several reasons but have encountered the following errors: 1) My PCB board has 2 HDMI ports configurable as sink/source, however when using 2 instances of the DVI2RGB core I get the following error: (error1.png) 2) I would like to make a generic data protocol around the HDMI connector that doesn't require blanking and the DVI2RGB core is a nice, open-source platform for me to experiment with new configurations. However, when repackaging the IP regardless of whether I make any changes I get the following error: (error2.png) For 1) I know I can solve my problem by modifying the IP (and probably just by adding a top-level constraint file to overwrite the dvi2rgb.xdc file), but because of the error in 2) I cannot accomplish this task. I have searched these forums as well as Xilinx with no luck regarding this problem. I have also searched through the Xilinx documentation (UG1118) on IP packaging, but was unable to find any useful information about something I may be doing wrong. I have also tried modifying the IP every way I can think of to remove the dependency on the board.xit file, but with no luck. If anyone has tried this or encountered similar problems with modifying any Diligent IP your advice would be greatly appreciated! Just to reiterate, I only really care about being able to repackage the dvi2rgb core myself, and the error above appears simply from editing the IP in the IP packager, leaving everything set as its default and repacking it. The first time I open the IP there is no implementation file group and the file utils/board/board.xit doesn’t exist, but when I repack it I get the error and when I reopen it in the ip packager again the file is there: (ippackager.png) Some info on my setup: I am running windows 10 64 bit, using vivado 2017.1 and have tried this with both dvi2rgb 1.6 and 1.9. If any additional information is needed please let me know. In the upcoming semester I will be helping mentor a group of undergraduate students on the contents of this IP, so resolving this before the semester starts would be a huge help. Best regards, Tyler Browning
  23. Shuvo Sarkar

    Adding custom IP in Zybo HDMI demo project

    Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  24. Shuvo Sarkar

    Video output at VGA monitor

    Dear experts, I am actually new in this field and have a very few experience with zybo board. I have implemented the zybo_hdmi_in_demo which is required for my master thesis. Output video streaming at the VGA monitor shows a cropped part of my input video source. What should I do now? And can I use other HDMI source rather than my PC? And what is the preferred input HDMI video resolution? any kind of support or suggestions is highly appreciated.
  25. M24

    dedicated HDMI ports on the Zybo Z7

    hello, The Zybo Z7 has 2 HDMI ports, RX and TX. On the Zybo you had one port which could serve as input or output. Since the PHY is still implemented in the FPGA I wonder what the advantages are with this change, because before you could have set the ports as input or output as you like.