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  1. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA se
  2. Hi, I want to create a test pattern generator project that uses the TPG IP to display the test patterns on the monitor via HDMI. For this I have been referring the Xilinx Video Series 19, however, the hardware used in the video is ZC702 and the hardware I am using is Zybo Z7-10. I also checked the HDMI demo available for Zybo Z7-10 but it does not include the TPG IP. Kindly suggest how can I achieve the same. I tried to replicate the block design from the video series 19 and made a few changes but I am not sure about it and got a few errors. I have attached the block diagram image an
  3. I've finally got my HDMI input project to a point where I have something to show. This little picture makes me really happy: This project does the following actions: Advertise HDMI support over EDID/DCCReceive the TMDS signalsDe-serialize them into 10-bit symbolsAlign the symbols using bitslipsTune the input delays for best receptionConvert the TMDS symbols into data valuesExtract CTL, Aux Data Periods (ADPs) and Video Data Periods (VDPs)Extract Video Infoframes from the ADP dataExtract Audio Samples from the ADP data.Extract Raw Pixels from the VDPsPerform 422 to 444 conversion, if required
  4. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how t
  5. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  6. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! 😃 Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride
  7. Tom G

    Genesys 2 HDMI demo

    Does anyone have the Digilent HDMI demo running on the most recent Xilinx IP cores / Vivado 2019.2? Upgrading the IP cores (necessary because I don't have a license to the old ones) seems to result in the bitstream generation failing and a ton of error messages that I can't see how to resolve. Any help much appreciated.
  8. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  9. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  10. Does the demo design ( support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  11. I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me.
  12. birca123


    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, T
  13. Hello, Is there any way that I can connect the Nexys4DDR to an HDMI connector, for example using a breakout board such as this one The critical factor would be getting access to 4 differential pair outputs (TMDS) from the Artix-7 FPGA. I note that there is no HDMI PMOD available, which suggests that these pins are actually not available externally on this board. I already have the Nexys4DDR, which is the right board for me. I don't need the dedicated Nexys Video, I'm just trying to upgrade my display output from VGA to HDMI - which could
  14. Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA ([email protected]). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are fro
  15. Dear Digilent Engineers, I am having a trouble when displaying images in the HDMI output. Although I tried to follow all the recommendations for the generation of the Zybo-base-linux project, the Linux kernel configuration and the devicetree, I had wrong colors and rendering in the HDMI output. I am using the Ubuntu based Linaro filesystem which comes with a graphical interface (I wonder it is the last version which have this feature). Do you know which element could produce this behaviour and which changes I could apply to correct it. I attach a screenshot and a photo of my HDMI scr
  16. I am using Xlinux ZYBO-7000 board with Debian Jessie Linux, the FPGA programming is done by my professor. as part of my project I have to display my PyQt5 application via HDMI, in order to display pyqt45 application via HDMI, I have to point PyQt5 application to framebuffer /dev/fb0. but it gives me "cannot connect to X server" error. I had used qt designer to create my GUI application in ubuntu16.4 and then I copy my project into ZYBO (Debian-Jessie). but then I find out that I have to compile pyqt5 with linuxfb then it will display GUI into framebuffer. but I do not know how to do
  17. Hello, I'm trying to make a standalone application for image processing on ZYBO, but I have problems with creating a block design which would make it possible. Since I started using Vivado two months ago, I'm still not familiar with creating my own block designs. I know that I should use dvi2rgb, Video In to AXI4-Stream and AXI VDMA IPs to store frames to DDR memory, but I don't know how to configure them. My idea is to create a function in Vivado SDK, e.g. CaptureImage(), which would return an address of the image saved in memory. Can somebody help me create the simplest block design
  18. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  19. Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for [email protected] like this: static const VideoMode VMODE_3840x2160a30 = { .label = "[email protected]", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which re
  20. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The compu
  21. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as
  22. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my
  23. Hello everyone, I've bought a Zybo Z7 with a XC7Z010. I've downloaded the HDMI demo (link here) and I got it working - I connected my laptop to the RX port and a monitor to the TX port. Now what I'm trying to do is to have the TX connected to a monitor, build an image using Petalinux and once I program the SoC I can see the Linux booting on the monitor. I've built an image using the bit and hdf files provided on the HDMI demo project and on Petalinux kernel config I've enabled the following: Device Drivers -> Graphics support -> Enable HDMI HDCP support in MSM DRM driver
  24. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used th
  25. Hello, i have got a problem with the output of a simple HDMI signal. I use the the IP block rgb2dvi of digilent and a vga.vhd file which creates the hsync, vsync signals. I connected the signals with vid_pHSync, vid_pVsync of the rgb2dvi IP. I created a vector (23 downto 0) with ('1') for vid_pData, with this vector is want show a white picture on the screen. The vid_pVDE is connected with '1'. I used the vga.vhd in a former project where i created a VGA signal on a screen. The vga.vhd creates a signal with 800 x 600 pix and 72Hz. The pixel clock is 50Mhz. What's the me