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Found 96 results

  1. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  2. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! 😃 Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Question 2 (pending): The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant. Some receivers get along with this signal but some unfortunately don't. To get a "true" 720p signal, pixel clock should be 74.25 MHz. Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ? Thank you very much for your help
  3. Tom G

    Genesys 2 HDMI demo

    Does anyone have the Digilent HDMI demo running on the most recent Xilinx IP cores / Vivado 2019.2? Upgrading the IP cores (necessary because I don't have a license to the old ones) seems to result in the bitstream generation failing and a ton of error messages that I can't see how to resolve. Any help much appreciated.
  4. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  5. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  6. Does the demo design (Zybo-Z7-20-HDMI-2018.2-1.zip) support 1920x720 HDMI path-throught? The Product guide for dvi2rgb and rgb2dvi IP mentions that "Resolutions supported: 1920x1080/60Hz down to 800x600/60Hz (148.5 MHz – 40 MHz)" but I am not sure if the specific resolution 1920x720 is supported. Thank you
  7. I have successfully compiled, flashed, and ran the hdmi in example project in the digilent github repo. However, no matter the hdmi source I use, I cannot get the hdmi to connect to the Zybo dev board. The CRT monitor is displaying the VGA output, and I can change resolution and frame buffers. However, I always get an !HDMI unplugged! error on the uart output. My windows machine recognizes the "monitor" and I can change the resolutions on the windows side of things, but no matter the resolution I cannot get the connection to go through. See attached screenshot. This is very frustrating for me. Any help would be appreciated. This is the 3rd or 4th tutorial/example I have tried since getting the board today. All in all everything has gone smoothly up to this point, but I have not the fpga/vivado experience to determine the issue. also my log output from vivado is attached. implementation.txt
  8. birca123

    ZYBO HDMI-IN

    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, Toni Birka
  9. Anding

    HDMI on the Nexys4-DDR?

    Hello, Is there any way that I can connect the Nexys4DDR to an HDMI connector, for example using a breakout board such as this one https://www.adafruit.com/product/3119 The critical factor would be getting access to 4 differential pair outputs (TMDS) from the Artix-7 FPGA. I note that there is no HDMI PMOD available, which suggests that these pins are actually not available externally on this board. I already have the Nexys4DDR, which is the right board for me. I don't need the dedicated Nexys Video, I'm just trying to upgrade my display output from VGA to HDMI - which could be a relatively simple job. Related to this, if I can post my request for the next version of the Nexys4 board: replace the VGA connector with a DVI connector and connect both the "VGA" pins and the "HDMI" pins from the DVI connector to the FPGA. Users can then either uses a DVI/HDMI cable or an DVI/VGA adaptor at preference.
  10. Finally working! Brief description: On right monitor is ssh session from my devel PC to Zyboz7-20 where I start Qt applications (framebuffer and sysinfo on attached picture). Front monitor is connected to ZyboZ7-20 HDMI output port. Monitor resolution is SXGA ([email protected]). FPGA: - Build with Vivado 2016.4 - Data path for HDMI output: /dev/fb0 DDR image buffer --> Zynq AXI HP port --> AXI Protocol Converter IP (AXI3 to AXI4) --> VDMA IP (mm2s only) --> AXI4 Stream to Video IP --> Digilent RGB to DVI IP --> HDMI connector Video control signals are from Video Timing Controller IP (1280x1024p, Pixel clock is 108MHz). On SD card: - Boot image containing: FSBL, U-boot (Xilinx git tag xilinx-v2017.3), LX 4.6 kernel (configured and build from Xilinx git tag xilinx-v2016.4) and Buildroot-2017.08.1 - Modified Simple FrameBuffer driver. - Xilinx DMA driver. - My custom driver to control FPGA modules (VTC, Xilinx Performance monitor and some others I have in design). - Cross compiled Qt-4.8.6 examples (analogclock, framebuffer) and Qwt-6.1.3 examples (sysinfo, cpuplot). TODOs: - Simple FrameBuffer driver does not starts Xilinx DMA driver transfers, so I have to configure VDMA IP registers manually. But this is good enough for my first run and proof of concept. I will switch to and continue with DRM device driver. - Inputs (mouse and keyboard) to control Qt application.
  11. Dear Digilent Engineers, I am having a trouble when displaying images in the HDMI output. Although I tried to follow all the recommendations for the generation of the Zybo-base-linux project, the Linux kernel configuration and the devicetree, I had wrong colors and rendering in the HDMI output. I am using the Ubuntu based Linaro filesystem which comes with a graphical interface (I wonder it is the last version which have this feature). Do you know which element could produce this behaviour and which changes I could apply to correct it. I attach a screenshot and a photo of my HDMI screen. I checked the cable and screen and those are correct. I also probed a precompiled image from the Zybot project and it shows a normal behaviour. However I need to add some modules to the base-linux so I have to compile it by myself. Hope you could help to solve with this problem. Thanks.
  12. I am using Xlinux ZYBO-7000 board with Debian Jessie Linux, the FPGA programming is done by my professor. as part of my project I have to display my PyQt5 application via HDMI, in order to display pyqt45 application via HDMI, I have to point PyQt5 application to framebuffer /dev/fb0. but it gives me "cannot connect to X server" error. I had used qt designer to create my GUI application in ubuntu16.4 and then I copy my project into ZYBO (Debian-Jessie). but then I find out that I have to compile pyqt5 with linuxfb then it will display GUI into framebuffer. but I do not know how to do it? I search on the internet but I could not found a solution. can anyone please suggest me so tutorial or something regarding how to run the pyqt5 application in zybo 7000?
  13. Hello, I'm trying to make a standalone application for image processing on ZYBO, but I have problems with creating a block design which would make it possible. Since I started using Vivado two months ago, I'm still not familiar with creating my own block designs. I know that I should use dvi2rgb, Video In to AXI4-Stream and AXI VDMA IPs to store frames to DDR memory, but I don't know how to configure them. My idea is to create a function in Vivado SDK, e.g. CaptureImage(), which would return an address of the image saved in memory. Can somebody help me create the simplest block design to accomplish that? Best regards, Toni
  14. Hello, I would like to know if there is any way to build this project on Vivado 2018.3? Or the easiest way would be uninstalling this version and installing Vivado 2016.4 to build it? Cheers.
  15. shurunxuan

    Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for [email protected] like this: static const VideoMode VMODE_3840x2160a30 = { .label = "[email protected]", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  16. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 2475.248 MHz (CLKIN1_PERIOD, net CLK) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y1 (cell hdmi_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (15.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. To get around, I edited the rgb2dvi_ooc.xdc such that I have commented out the following: #create_clock -period 6.060 [get_ports PixelClk] #create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] But it didn't help. What more can I do? Suggestions, advises? I have attached the top level xdc. hdmi_vdma.xdc
  17. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as provided in file Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its specific part edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) i have attach xdc file and desing image i m using zybo board having specific xc7z010clg400-1 part pls provide some solution or any other help ASAP Zybo_B.xdc
  18. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben
  19. Hello everyone, I've bought a Zybo Z7 with a XC7Z010. I've downloaded the HDMI demo (link here) and I got it working - I connected my laptop to the RX port and a monitor to the TX port. Now what I'm trying to do is to have the TX connected to a monitor, build an image using Petalinux and once I program the SoC I can see the Linux booting on the monitor. I've built an image using the bit and hdf files provided on the HDMI demo project and on Petalinux kernel config I've enabled the following: Device Drivers -> Graphics support -> Enable HDMI HDCP support in MSM DRM driver -> Xilinx DRM -> Xilinx DRM Display Port Driver -> Xilinx DRM Display Port Subsystem Driver I can program the SoC ok but I get no output on the monitor. Am I missing something? Thanks in advance!
  20. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used the diligent dvi2rgb and rgb2dvi IPs. Have used a PLL (not MMCM) to generate the ref_clk (125MHz is board input and the PLL produces the 200MHz clk required delay taps). I have attached my top level VHDL file which shows the connections. I have also attached the XDC file. Note that in the XDC I have changed the tmds_rx_clk frequency to 80MHz which is suitable for a HDMI data source with 720p resolution (else there will be Impl errors as the Z7-10 has a -1 speed grade FPGA). Bit stream was successfully generated without timing errors. The synth design is as shown below. The design is not working after I have downloaded the bitstream. So the most important question is if the above makes sense? If the above is rubbish, then what can I do to improve my design? I just want to pass HDMI data from Rx port to the Tx port. Do I need to do some buffering of the pixel data (3 FIFOs for each channel with 8bits width, depth - I don't know ) before connecting vid_pData from dvi2rgb to rgb2dvi? Else what would help? Any help/suggestions are appreciated. Regards. hdmi_pass_top.vhd hdmi_pass.xdc
  21. Hello, i have got a problem with the output of a simple HDMI signal. I use the the IP block rgb2dvi of digilent and a vga.vhd file which creates the hsync, vsync signals. I connected the signals with vid_pHSync, vid_pVsync of the rgb2dvi IP. I created a vector (23 downto 0) with ('1') for vid_pData, with this vector is want show a white picture on the screen. The vid_pVDE is connected with '1'. I used the vga.vhd in a former project where i created a VGA signal on a screen. The vga.vhd creates a signal with 800 x 600 pix and 72Hz. The pixel clock is 50Mhz. What's the meaning of the vid_pVDE signal...?? My problem is that i dont get a signal on the screen...?? Have a nice day...Bye bye project_6.srcs.zip
  22. hello, can I change the reference clock for Dynamic Clock Generator IP core? Which frequency do I have to provide for REF_CLK_I?
  23. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?
  24. i want to work on a video project which board will be better zybo or pynq . as i have studied that pynq has unbufferd hdmi. suggestions will be highly appreciated. Thanks
  25. I'm starting in the FPGA world and would like to know what the best digilent FPGA solution for HDMI projects. What I intend to do is a split monitor. Where two incoming HDMI signals are displayed on a single monitor. Arty A7: Artix-7 FPGA Development Board for Makers and Hobbyists is it enough for this project? thanks