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Found 86 results

  1. Dear Digilent Engineers, I am having a trouble when displaying images in the HDMI output. Although I tried to follow all the recommendations for the generation of the Zybo-base-linux project, the Linux kernel configuration and the devicetree, I had wrong colors and rendering in the HDMI output. I am using the Ubuntu based Linaro filesystem which comes with a graphical interface (I wonder it is the last version which have this feature). Do you know which element could produce this behaviour and which changes I could apply to correct it. I attach a screenshot and a photo of my HDMI screen. I checked the cable and screen and those are correct. I also probed a precompiled image from the Zybot project and it shows a normal behaviour. However I need to add some modules to the base-linux so I have to compile it by myself. Hope you could help to solve with this problem. Thanks.
  2. shurunxuan

    Zybo HDMI output help

    Hello everyone, I'm new to Zybo board and I have a question about it's HDMI port. Is Zybo's HDMI port capable of 3840x2160 video signal output at either 30fps or 60fps? If so, how should I modify the HDMI TX demo? I tried to add timing parameters for 3840x2160@30fps like this: static const VideoMode VMODE_3840x2160a30 = { .label = "3840x2160@30Hz", .width = 3840, .height = 2160, .hps = 4016, .hpe = 4104, .hmax = 4400, .hpol = 1, .vps = 2168, .vpe = 2178, .vmax = 2250, .vpol = 1, .freq = 297 }; But I always get 240MHz pixel clock frequency when the program runs, which results in "no signal" on my monitor. I guess this requires a change in the block diagram, but I need help on it. Thanks!
  3. Hello all, I have got hold of the Digilent Zybo Video Workshop, Paris, France, 23.03.2017 PDF. I am following "Task Two" there in, at page 16 - Create a pass-through video pipeline. I want to implement this using a Z7-10 and using Vivado 2017.4. I will be using 720p resolution video (TMDS input clock < 80MHz). I have build the BD and is as shown below. This you can find in the PDF at page 26 and is exactly the same. The design is synth properly but during bitstream generation I get the following error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 2475.248 MHz (CLKIN1_PERIOD, net CLK) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y1 (cell hdmi_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (15.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. To get around, I edited the rgb2dvi_ooc.xdc such that I have commented out the following: #create_clock -period 6.060 [get_ports PixelClk] #create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] But it didn't help. What more can I do? Suggestions, advises? I have attached the top level xdc. hdmi_vdma.xdc
  4. Gourav

    zybo hdmi to vga out

    Hello to all, i have start working on video processing through zybo board,so for that i have gone to digilent zybo video workshop file, its link is provided below i gone through all steps carefully make all connection as shown in file but still nothing show Changes i have done in ip clocking wizard ip : sys_clock take 125mhz freq and set to mmcm at 200 mhz output dvi2rgb1v_7 ip : preferred resolution 1280*720 and other option as guided in file and other ip changes as provided in file Regarding error: their is no error or any critical warning is shown in vivado 2016.2 version bur still nothing shows,even though i have provided external power supply 5v to it and change jumper to its specific part edge detetion works fine and show rover output so i imported it in design and the complete design image i add in attachment.( i have twice check the hdmi cable ,vga projector and lp output all works fine) i have attach xdc file and desing image i m using zybo board having specific xc7z010clg400-1 part pls provide some solution or any other help ASAP Zybo_B.xdc
  5. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! =) Question 1: I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000. If I look at the MPMC configuration, its base address parameter is set to 0x48000000. I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ? Thank you very much for your help
  6. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben
  7. Hello everyone, I've bought a Zybo Z7 with a XC7Z010. I've downloaded the HDMI demo (link here) and I got it working - I connected my laptop to the RX port and a monitor to the TX port. Now what I'm trying to do is to have the TX connected to a monitor, build an image using Petalinux and once I program the SoC I can see the Linux booting on the monitor. I've built an image using the bit and hdf files provided on the HDMI demo project and on Petalinux kernel config I've enabled the following: Device Drivers -> Graphics support -> Enable HDMI HDCP support in MSM DRM driver -> Xilinx DRM -> Xilinx DRM Display Port Driver -> Xilinx DRM Display Port Subsystem Driver I can program the SoC ok but I get no output on the monitor. Am I missing something? Thanks in advance!
  8. Hello, I am trying to build a hdmi pass-through project using Z7-10 and Vivado 2017.4 as IDE. Intention: To demonstrate whether the Z7-10 board can rx hdmi signals (from my PC hdmi out) and display the same on an hdmi monitor. I don't intend to do any processing on the data. Only PL is to be used, no PS. Structure: HDMI source(720p) --> Z7-10 HDMI Rx port/connector --> dvi2rgb IP --> rgb2dvi IP --> Z7-10 HDMI Tx port/connector --> HDMI monitor Now I am not sure if the above architecture makes sense in order to build a hdmi pass through. I have used the diligent dvi2rgb and rgb2dvi IPs. Have used a PLL (not MMCM) to generate the ref_clk (125MHz is board input and the PLL produces the 200MHz clk required delay taps). I have attached my top level VHDL file which shows the connections. I have also attached the XDC file. Note that in the XDC I have changed the tmds_rx_clk frequency to 80MHz which is suitable for a HDMI data source with 720p resolution (else there will be Impl errors as the Z7-10 has a -1 speed grade FPGA). Bit stream was successfully generated without timing errors. The synth design is as shown below. The design is not working after I have downloaded the bitstream. So the most important question is if the above makes sense? If the above is rubbish, then what can I do to improve my design? I just want to pass HDMI data from Rx port to the Tx port. Do I need to do some buffering of the pixel data (3 FIFOs for each channel with 8bits width, depth - I don't know ) before connecting vid_pData from dvi2rgb to rgb2dvi? Else what would help? Any help/suggestions are appreciated. Regards. hdmi_pass_top.vhd hdmi_pass.xdc
  9. Hello, i have got a problem with the output of a simple HDMI signal. I use the the IP block rgb2dvi of digilent and a vga.vhd file which creates the hsync, vsync signals. I connected the signals with vid_pHSync, vid_pVsync of the rgb2dvi IP. I created a vector (23 downto 0) with ('1') for vid_pData, with this vector is want show a white picture on the screen. The vid_pVDE is connected with '1'. I used the vga.vhd in a former project where i created a VGA signal on a screen. The vga.vhd creates a signal with 800 x 600 pix and 72Hz. The pixel clock is 50Mhz. What's the meaning of the vid_pVDE signal...?? My problem is that i dont get a signal on the screen...?? Have a nice day...Bye bye
  10. hello, can I change the reference clock for Dynamic Clock Generator IP core? Which frequency do I have to provide for REF_CLK_I?
  11. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?
  12. i want to work on a video project which board will be better zybo or pynq . as i have studied that pynq has unbufferd hdmi. suggestions will be highly appreciated. Thanks
  13. I'm starting in the FPGA world and would like to know what the best digilent FPGA solution for HDMI projects. What I intend to do is a split monitor. Where two incoming HDMI signals are displayed on a single monitor. Arty A7: Artix-7 FPGA Development Board for Makers and Hobbyists is it enough for this project? thanks
  14. can we use output from python code in verilog on pynq board. e.g if we take hdmi in python. Can we process that frames in verilog.? Thanks
  15. I'm trying create a PL subsystem that takes a HDMI video in and outputs it on the VGA. I got the digilent IP from this github and I created a HDMI in to VGA out loop in Vivado as shown below I have set the clock wizard up to provide 200MHz to the dvi2rgb block and the clock wizard block has an input clock 125MHz. I programmed the dvi2rgb block with the following config After trying to generate the bitstream for this I'm getting critical errors at the implementation stage saying it can't meet timing. It managed to generate the bitstream but its output an video from the VGA. Any ideas what is causing these timing errors? or where I am going wrong with the implementation? ZYBO_Master.xdc.txt
  16. Hello, New to this forum and my first post. I want to run the HDMI demo by following this: However this is for Vivado 2016.4 . Now I want to modify the TCL script so that I can run this DEMO using Viv2017.4. I have run into problems while trying to run it directly (if needed I post the error details). 1. Does a migrated project already exists? 2. If <1> is false, then how can I migrate the TCL script? Any guidelines, references? Thanks.
  17. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link: And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  18. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: CSI-2 Camera: DLP 2000 RGB - projector: HDMI projector: Display : Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  19. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link: And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  20. Hi, Does anyone know if/where I can find an AXI4 example running on Atlys similar in functionnality to the HDMI PLB demo ? The example would show how to read frames from HDMI in, store to memory via AXI4 VDMA core, and read from memory to HDMI out. Thanx !
  21. Hello, I am trying to initialize the ADV7611 Chip of the Digilent FMC-HDMI add-on Board. But I can't find the needed addresses for it (this doesn't help). I am using the xiic.h Driver from xilinx. The initalization of ADV7511 Chip of the zc702 was successfully. Have anyone a idea?? I am using the zc702 and the digilent FMC-HDMI Card.
  22. Mohammad Ahmad


    FMC-HDMI can work at 1080p@30fps/24bit RGB and 720p@60fps/24bit RGB (HDTV)?
  23. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  24. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  25. Hi all Here is a quote from Wikipedia's page on HDMI "HDMI permits sRGB 4:4:4 chroma subsampling (8–16 bits per component), xvYCC 4:4:4 chroma subsampling (8–16 bits per component), YCbCr 4:4:4 chroma subsampling (8–16 bits per component), or YCbCr 4:2:2 chroma subsampling (8–12 bits per component). The color spaces that can be used by HDMI are ITU-R BT.601, ITU-R BT.709-5 and IEC 61966-2-4." I have a video in 8 bit 480p YCbCr 4:2:2 format sitting in BRAM, and I want to output it with HDMI. I have a Zybo Z7-20 board. Is there a way to output the data directly without converting to other color spaces. If I do have to convert, than can someone explain the process that needs to be done, both in theory and in practice? This person seems to think that HDMI is simple enough:, but he has 4:4:4 RGB. EDIT: I thought about it a little more...It could be that switching to another color space is not 'my problem'. It could be the receiver's responsibility. Meaning that the HDMI screen has to be told to be prepared to receive YCbCr 4:2:2... If this is the case, in what format do I send my data to the HDMI port...what does it expect... HDMI has three differential data lines, a clock, VCC and ground, (the rest I can ignore) so I assume it gets serial data... Anyone with any ideas, anything to add/fix... EDIT 2: Here is a quote from the HDMI protocol "Video data is carried as a series of 24-bit pixels on the three TMDS data channels. TMDS encoding converts the 8 bits per channel into the 10 bit DC-balanced, transition minimized sequence which is then transmitted serially across the pair at a rate of 10 bits per pixel clock period." I did not understand all of this, but I think it means that the data is sent at 8 times the rate as the clock... so maybe its not as simple as I thought... still welcoming words of advice...