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Showing results for tags 'hdmi demo'.
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Hi, I have a lot of problem importing project. I had imported HDMI project and I use zybo board. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start When I started create_project.tcl vivado get me critical errors, so I decided to enter commands manually. I had errors because on create_project.tcl there aren't commands to upgrade the IP blocks. I have resolved it. now i have 193 warning and 1 critical warning (table1.xlsx file): [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. Can you help me to correct this? I can generate bitstream but i have a problem. After I had exported hardware and i had launch sdk I need to import project. I have so many errors!!!!! I attach sdk log txt file. There is a big problem on include folder on the left menu. I had try to add on HDMI_IN_bsp the ps7_cortexa9_0 folder that I have found in a forum , I have deleted hdmi-in.sdk folder from my project, and I try again export hardware, launch sdk, import project. I have resolve the problem of include folder on left menu but still I have problems with libraries. I think there are some compatibility problems in the project on Vivado 2017.1. Do you know how i can fix it? Can you update the project? Thanks Andrea Table1.xlsx sdk log.txt
Hi FPGA gurus ! I'm trying to achieve video processing with Atlys board. My goal is to real-time rotate some VGA Stream (640x480@60) form hdmi input to 720p hdmi output. Rotation is 90° clockwise. The attached picture sketches what i'm aiming at. I've been thinking of using HDMI Demo project for this. I am a total noob to all this FPGA thing, i'm slowy trying to learn but it's not that simple when you don't know anything about electronics =) From what I have understood, in the HDMI demo the frame in written to DDR2 memory with a single call to the VFBC. TMDS data is pushed in the FIFO and when a new frame is detected, then the Write Command is emitted and stores the whole frame to memory. I thouht a good design for my project would be to store line by line, configuring the VFBC command with X=1, Y=639 and BaseAdress = [(40*lineStride)+(1160-lineCnt)] * 2. This way : line 1 (blue) is stored in the frame buffer as a 1 pixel wide column starting at pixel (1159,40) line 2 (green) is stored in the frame buffer as a 1 pixel wide column starting at pixel (1158,40) ... line 640 (orange) is stored in the frame buffer as a 1 pixel wide column starting at pixel (680,40) My understanding of the HDMI Demo is that modifying user_logic.vhd in hdmi_in is all i have to do, so that instead of writing the whole frame in one vfbc command, the frame should be written line by line with 640 VFBC commands, one for each line, with constant width = 1, constant height = 639 and baseAdress computed as shown above. Is this correct ? Any Suggestion, hint, advice or help will be highly appreciated as I quite lost with this !! Cheers
Hello everyone, I'm a beginner at Vivado. I am using Vivado 2016.4 and the Nexys Video Board. I've been trying for some days to generate the bitstream for the HDMI-Demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-hdmi-demo/start). But after creating the project with the tcl console I got the error message that some IPs (hdmi_axi_dynclk_0_0, hdmi_rgb2dvi_0_0, hdmi_dvi2rgb_0_0) are locked. So I already upgraded them but now I get the following error messages and have no idea how to solve it. [Synth 8-3302] unable to open file '900p_edid.txt' in 'r' mode [EEPROM_8b.vhd:90] [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [EEPROM_8b.vhd:115] [Synth 8-285] failed synthesizing module 'EEPROM_8b' [EEPROM_8b.vhd:85] [Synth 8-285] failed synthesizing module 'dvi2rgb' [dvi2rgb.vhd:110] [Synth 8-285] failed synthesizing module 'hdmi_dvi2rgb_0_3' [hdmi_dvi2rgb_0_3.vhd:80] [Synth 8-285] failed synthesizing module 'hdmi' [hdmi.vhd:5987] [Synth 8-285] failed synthesizing module 'hdmi_wrapper' [hdmi_wrapper.vhd:49] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details I already looked at the forum here and consulted google, but found no solution or a similar problem there. Does anyone of you solved this problem already or has an idea how to solve it? I would be very thankful for any kind of idea.