Search the Community

Showing results for tags 'hdmi demo'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Test and Measurement
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 6 results

  1. I have problems with HDMI demo on ZYBO Z7-20, The demo runs well but the resolutions are not correct its kind of crops the stream, the other problem is that on photos and videos red lines appear on edges of the objects and gradients, this happens on videos and photos and not on text, for example if I watch a youtube most of corners of objects get this red lines and other texts for example video description looks normal
  2. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it del
  3. I'm following along with the instruction provided on the GitHub (https://github.com/Digilent/Zybo-Z7-10-HDMI/blob/master/README.md) to test the functionality of the Zybo board's HDMI ports. I followed the instruction to the T but cannot seem to get a signal to pass through. At first, I connected my cable box to the HDMI Rx and then I switched to my laptop. In both instances, not only did my TV monitor not detect a signal, but the output on the sdk terminal was that the HDMI-in was unplugged (see first attached photo). The HDP / LD9 LED near the HDMI port turns on, telling me it is detecting a
  4. Hi, I have a lot of problem importing project. I had imported HDMI project and I use zybo board. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start When I started create_project.tcl vivado get me critical errors, so I decided to enter commands manually. I had errors because on create_project.tcl there aren't commands to upgrade the IP blocks. I have resolved it. now i have 193 warning and 1 critical warning (table1.xlsx file): [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for d
  5. Hi FPGA gurus ! I'm trying to achieve video processing with Atlys board. My goal is to real-time rotate some VGA Stream ([email protected]) form hdmi input to 720p hdmi output. Rotation is 90° clockwise. The attached picture sketches what i'm aiming at. I've been thinking of using HDMI Demo project for this. I am a total noob to all this FPGA thing, i'm slowy trying to learn but it's not that simple when you don't know anything about electronics =) From what I have understood, in the HDMI demo the frame in written to DDR2 memory with a single call to the VFBC. TMDS data
  6. Hello everyone, I'm a beginner at Vivado. I am using Vivado 2016.4 and the Nexys Video Board. I've been trying for some days to generate the bitstream for the HDMI-Demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-hdmi-demo/start). But after creating the project with the tcl console I got the error message that some IPs (hdmi_axi_dynclk_0_0, hdmi_rgb2dvi_0_0, hdmi_dvi2rgb_0_0) are locked. So I already upgraded them but now I get the following error messages and have no idea how to solve it. [Synth 8-3302] unable to open file '900p_edid.txt' in '