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Found 22 results

  1. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the featured device very very carefully to make sure that it can do what you want it to do. This is not nearly as simple as you would think, especially for ADC devices where specmanship, little white ( sometimes closer to black ) lies, and covering up 'features' that might render the device useless for your requirements has always been the rules of the road. Pore over the schematic for the EMV and trace every pin through the connector to ensure compatibility with your FPGA board. Pay particular attention to power supply pins. Download the supporting software, when available, and understand what you get or don't. Understand that good ADC interfaces, on the analog side, tend to be very application specific. The ADC demo boards tend to be general purpose; but not always. Not listed below is the ADS4449 EVM that I managed to get working with the KC705 board a number of years ago. This 4 channel high speed ADC EVM is set up for narrowband processing of signals centered around 185 MHz. It served it's purpose but I can't recommend it. HSMC compatible boards. ADC/DAC Linear Technology DC2459A LTC1668 16-bit 50 Msps DAC This is one of those rare EVMs designed to connect to an FPGA development board. It can connect directly to a board with an HSMC connector, a DE0 Nano, a Mimas or Mojo board. Mine is always attached to a DE0 Nano and ready to go. I use an external TTL USB UART for control. The DE0 Nano is a cheap and very handy board to have around. ( If only it had a nice Artix FPGA... not that I have anything against the Cyclone V ) Linear Technology DC2390A for LTC2500-32. 2 LTC2500-32 32-bit ADCs and 2 LTC1668 16-bit 50 Msps DACs Connects to any FPGA board with an HSMC connector. The EVM is intended to be used with the Cyclone V SoCkit and has slick software support if used with this ARM based board. I prefer rolling my own interface and using another FPGA platform. Interesting approach o the software side. Terasic makes a couple of not too expensive ADC/DAC HSMC compatible add-on boards. I've already posted a description of a demo project that I completed ( well as far as I need to for now ) recently showing one way to use the Ethernet PHY to make use of such boards. In recent years I've really lost my enthusiasm for low end Intel FPGAs and Quartus tools so that post isn't as silly as you might assume that it is. USB 3.0 Both FTDI and Cypress offer reasonably priced development kit options for using their USB 3.0 interface devices for both HSMC and FMC connector equipped boards. In fact for the FMC versions these are among the only inexpensive mezzanine boards that you will find. I much prefer the flexibility of the Cypress FX3 but be aware that you need to do some embedded ARM development and there's a steep learning curve. If you want to learn about USB this is the way to go. FMC compatible boards. The FMC ecosystem is, with few exceptions, a very expensive place to play in. However on rare occasions you can get lucky. Understand that none of the boards below were intended to connect directly to an FPGA development board. Analog Devices EVAL-AD7761FMCZ AD771 8-channel 16-bit Simultaneous Sampling ADC. I've used this board with the Nexys Video with minimum effort. This is one of those devices where you can be very disappointed if you don't completely understand everything in the data sheet. Analog Devices EVAL-AD7616SDZ AD7616 16-Channel DAS Dual Simultaneous Sampling ADC. This board requires a SDP-I-FMC interposer. I didn't complete a project using it but haven't run into any obstacles hardware-wise. This is another device that requires very careful scrutiny before deciding that you want to spend your time or money on it. ** This advice also applies to FPGA boards that you are thinking of purchasing. If you want to use a particular feature, say DDR, find out if the vendor offers a usable demo showing how you might use it for your project. Find out if you need an evaluation license to build the demo for yourself in order to use that feature. There's only one way to do this... Before making a purchase install Vivado or ISE and see if you can actually build the demo projects for a board. Support, support, support. So what kind of support is provided for the board that you are interested in? Digilent is all over the place here. A very few boards have demo projects with HDL sources. One such board is the Nexys 7-A100T (Nexys 4 DDR) that has an OOB with VHDL sources for most of it's features. It does have a few IP .xco files that are supposed to work with Vivado 2018.2. I was unable to use the sources to generate a bitstream using Vivado 2018.2 SP1. ( I don't have the board so I didn't spend a lot of time trying only because I wanted to look at the DDR IP to reply to a posted question regarding DDR performance. Companies can pretend to offer more support than they really do by offering board design Xilinx IP flow demos. I personally, want to see HDL source as a measure of commitment to a product. Even though Digilent has shown that it's possible; it's hard to mess up an HDL demo. If there's very little in the way of providing build-able demo projects for board features or it take years to provide a reasonably accurate User's Manual these are big red flags. It doesn't mean that the board is useless, just that you had better have the experience and skill, and most importantly for me the time to write your own interfaces Tips for beginners. Not everything that board or even IC vendor makes is wonderful. If they spent money developing a product then they sure will try to find a customer to pay for those development costs. Sometimes, the only way to identify the dirty little secrets is to observe what's missing in a data sheet or sales blurb. If a normal feature is usually highlighted for most similar products and noticeably absent for the one that you are eyeing then this is a big red flag. What's missing is sometimes more informative than what's stated.
  2. kvantumnuly

    Genesys 2 - traces for GTX/gerber files

    Hi all, Is the gerber file for the Genesys 2 board available to the public? Or can you tell me location of traces between FPGA/FMC? I see eight traces with meandres, are the traces for GTX? Thank you.
  3. kvantumnuly

    Genesys2 - transceivers capability

    Hi all, was Genesys 2 board tested for a maximum transceivers capability (10.3125 Gbps)? Thanks for reply. Tomas
  4. OscarBarajas

    Genesys2 vs KC705 in terms of FMC connectivity

    Hi all, We are a small startup looking for an pga development platform. We need a fast ADC/DAC FMC board and right now we're looking at the fmc163 from abaco The board needs an FMC connector that conforms to the ANSI/VITA57.1 standard. I called Abaco and they confirmed it works with the Xilix KC705 kit via this adapter but couldn't confirm compatibility with the genesys2 board directly. I couldn't find any information as to if the genesys2 actually supports high speed ADC boards through the vita57.1 connector or not. Given that both boards seem to use the exact same FPGA (XC7K325T-2FFG900C) It is very important for me to know if it will work. Thank you.
  5. Hello everyone, I need suggestion about following topic: 1) I want to use an external oscillator 54 MHZ. And I want to take input this clock by FMC connector HA/LA pair (3.3 V) of genesys2 board. Is it will be ok? 2) The fixed oscillator 200 MHZ in Genesys2 is differential. I am producing my master clock for my design by MMCM. How can I have the minimum jitter? Any suggestion will be very helpful. Thank you Rappy Saha
  6. spike556

    genesys2 flash problem (help me pls..)

    i am a student. my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification) i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that. but the instruction is always 0x00000000 !! (i used chipscope to detect the signal) (i used startupe2 to access CCLK) it seems like i didn't access the flash, can anyone help me? thanks a lot !! pls save me....
  7. marco_pavesi

    DisplayPort on Genesys2 OOB project does not work

    Hi everybody I have a problem with the downloaded OOB design for Genesys 2: the DisplayPort seems to be properly configured, but the video does not appear. (It is not an issue related with the board, because the OOB stored on the flash of Genesys2 perform perfectly). I downloaded the design from the GIT (, dated 2017 March 18. Another ZIP is available, dated today (2017 May 2), looking inside they seems equivalent. Both designs are the previous version of the OOB, updated to Vivado 2016.4 and SDK 2016.4 So, I created the Vivado 2016 project, I asked for the proper evaluation licenses, and I achieved the bitfile. without particular problems. Then, I exported the HW to SDK, and I tried to import the sdk project/BSP (g2demo and g2demo_bsp) according to the instructions. I had a lot of errors. So, I generated a brand new BSP, with all driver updated, and I compiled the application. Everything fine. I downloaded to the board, and everything performs OK.... except DisplayPort. Console messages seems ok, the presence IRQ works, the DP is correctly trained and the screen is properly configured.... and nothing is shown. (By the way, VGA and HDMI works perfectly). Console messages are reported in screen.png I noted that the BSP delivered is really,really outdated. I tried to "patch" a .mss with the same outdated versions, but I had (as expected) a lot of bugs. Difference on versions are shown in drivers.png. Then I tried to keep the brand new BSP, and to outdate only the dp driver. It compiled, fine, but the behaviour is exactly the same. Now, I have some difficulty to proceed. It seems that the BSP you deliver is outdated, and it seems very strange. May you check your distribution, or, if correct, please give me an help about how to have correct compilation. Many thanks in advance, Marco Pavesi.
  8. marco_pavesi

    Genesys2 displayport OOB SDK 15.4

    Dear all I prepared yesterday evening an SDK 2015.4 project, to be used with the bitfile, hdf and bmm generated by Vivado 2016.4. This way there is a discrepancy between HW and SW version, but if it works who care. Unfortunately, the elf behaves as the design recompiled under SDK 2016.4. Additionally the display link seems less stable, it continuates to disconnect and connect The connection is correct. MArco.
  9. To cap off the Differential PMOD Challenge Project I present a project that uses the HDMI interface. This is the Genesys2_DDR design with real clock capable pins, buffered IO, and a high speed connector over a 1 meter cable. Data transfer rate goes from under 57 MB/s to over 230 MB/s. And, we can double that with a bit more effort. If you've been following the Differential PMOD Challenge discussion then you'll want to look at this project. If you work for Digilent then please read on....
  10. Hi, I am using genesis 2 board for my ongoing project. For flash programming, I have followed this tutorial. But now I am using Microblaze that's why I need to use SDK. But, I don't know how store SDK project into flash. I followed the "Getting started with Microblaze". But, If I want to upload the whole project to the flash what should I do? So, when I power up the Genesys 2 and connect the UART port by terminal application (Teraterm), The program will boot up from the flash and display the "Hello world" on the terminal display. Any suggestion will be very helpful. Thanks.
  11. zygot

    Transceiver Boot Camp

    Are you interested in trying out a 10.8 Gbps 4-lane data interface on your Genesys2 board? Try spending some time in Transceiver Boot Camp. You won't be disappointed.
  12. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy
  13. natsfr

    Genesys 2 FMC trace length

    Hello, I'm designing a custom FMC board to use with my Genesys 2. Is there any informations about GTX and serdes pair length ? Thanks
  14. I am working on Genesys 2 board for a while using Vivado 16.1 on Windows 10. It worked fine until yesterday. After rebooting my PC SDK/ Vivado is not detecting FPGA. I am not what has gone wrong suddenly. Please Help D
  15. Hi, I am using block memory generator 8.3 in vivado16.2. I am using to store my image sensor data. The resolution of the sensor is 1280*1024(=1310720). And each pixel contains 16-bit. Parameters I am using: Interface type: Native, Memory type: Simple Dual port RAM. PORT A is used for writing the pixels into the memory block. PORT B is used for reading out. Port A Width: 16 Range: 1 to 4608 bits (as each pixel has 16 bit) Port A Depth: 1310720 Range: 2 to 1048576 ( but this value exceed the range) So, I am thinking to write two pixels into the memory at a time so that I can reduce the Depth at half. Port A Width: 32 Range: 1 to 4608 bits Port A Depth: 655360 Range: 2 to 1048576 But it gave me some collision error which is shown in the attached image. But, I gave the value within the range. How can I allocate memory for my case? And what is the reason behind this error? Any suggestion will be appreciated. Thank you.
  16. rappysaha

    Simple code for DDR3 SDRAM

    Hi, I am very new at field of FPGA. Now I am working Genesys2. I have to control DDR3 memory. I find some examples in Digilent site for DDR3 using microblaze processor. But, in my case I don't have to use microblaze processor. I have to send some fixed value through the DDR3 memory like 8-bit data (X'FF') i.e. I will write that data into the Genesys2 DDR3 memory and readout the data from the memory. I already go through Xilinx manual ug_586 . But still it is not clear to me how to start coding for the DDR3 memory. My questions are: 1) Is it possible to have example code without using microblaze processor for DDR3 memory? Or any suggestion for starting code to control DDR3 memory. Actually, I have do it in any way. So any helpful suggestion will be appreciated. Thank you.
  17. Hi, I am using currently Genesys 2 board to interface my image sensor board. I want to connect image sensor board through the FMC connector of Genesys 2 board. Image sensor board is interfaced with C)N/FMC-ASP-134488. I have 12 timing signal pins in the sensor board, which are assigned to connect at serially pin no. K17, K20, K23, K25,K26,K28,K29,K31,K32,K34,K35,K38. (The pins are marked at attached schematic file of Genesys 2). My problem is when I am going to assign K17,K31,K32,K34,K35,K38 pins in the XDC file of the Genesys 2, I did not find these pins in the XDC file. Besides, I also tried to assign pins by RTL analysis (Elaborated design). But, in there these pins are also showing as invalid package pin. (the . XDC file is also attached here) So, how can I assign these pins in XDC file? OR it can not be used as I/O pin? Besides, I have 14-bit data output from the sensor board. Can I connect these 14-bit data pins directly to the FMC connector of the Genesys 2? I saw in the schematic of FMC connector I/O pins are differential. Is it will be a problem? Any suggestion will be appreciated. Thanks. Genesys2_H.xdc
  18. Hello, I'm a baby engineer. I want to write a binary user data file as well as a fpga configuration file in flash memory, Genesys2. I did it to Atlys board using a Adept software (you know It included the flash writing function!) in very easy way. But Genesys2, doesn't work. What can I do in order to write the user data to a desired start address like 0xA0000. in Vivado. or I just wait to the update Adept..?
  19. Ajinkya_Bankar

    Requirement of .ucf file

    Dear sir, I am working on Genesys2 board. I want pin locations of all peripherals such as I/O switches, LEDs, VGA connector, etc. Please give me .ucf file for all the peripherals available on the Genesys2 board. Thank you.
  20. Jensen

    Genesys 2 FT2232H

    Hello, I have a Digilentinc Genesys 2 board, my project needs to communicate between a PC and the FPGA. Because the data needs to travel at high speed I use the FT2232H-chip. I already can send data from the pc to the FPGA. But sending data from the FPGA to the PC isn't possible. My code(Verilog and Labview) works with a custom board with the same FT2232H-chip but not with the Genesys2. The problem is that the USB_TXEN doesn't go LOW. Is it possible that I need to set the USB-jumper(s) on another position? Does anybody know another source of this problem? With friendly regards, Jensen
  21. hamster

    Genesys2 PMOD A&B XDC file error

    Hi, I've been using the constraints file from and from debugging the pins for JA seem to be wrong set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3] set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] should really be set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] The low half seem to have the same problem too. The _p is connected to pin 1, 3, 7 or 9, and the _n is connected to pins 2,4,8 or 10 Looks like JB is the same too! Mike
  22. hamster

    Fractals on Genesys2.

    I've got my 1080i real-time fractal design running on the Genesys2 board, and the source checked in at - I spent last night getting rid of the 8-bit colour look, using the HDMI's 24 bit range.It uses about 100k flip-flops, 150k LUTs and 640 DSP slices, so uses a large chunk of the FPGA. If anybody is after a reference point, the Kintex-7 FPGA on the Genesys2 added 0.670ns slack to the 225MHz design that just meets timing on he Artix-7. But I can't make can't make use of the extra speed as the calculations run at a multiple of the pixel clock. The logic was also fast enough that I could implement 20% of the multipliers using LUTs - allowing me to get to 255 iterations in real time.