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  1. It's not easy adding Analog to your Digital for non-audio applications on a typical FPGA development board. I thought that some of you might find my experiences with the following useful. All of the following can be found from a distributor like Mouser or Digi-Key. You have to be careful because, especially for high speed ADC/DAC EVMs a lot of boards have HSMC and FMC type connectors that aren't compatible with the standard interfaces. Sometime you can cobble up a work-around but usually not. Before spending any money on an EVM you need to do this**: Read the data sheet for the feat
  2. Hi, I have a RISC-V design implemented on the Genesys2, with a UART that currently works through the USB-UART microUSB port, which just uses the uart_rx and uart_tx lines. I would like to send the UART output through the PmodBT2 to my Mac instead (connect via "screen" command in a terminal). From the Nexys 3 FPGA reference design, I believe I should connect the my uart_tx port to RXD pin on the PmodBT2, and uart_rx to TXD. I have done this and programmed the FPGA, and also established a connection to PmodBT2 from my Mac. However, when I run a hello world, I don't see any output in my term
  3. Hello, Could you please elaborate on this: "... for a limited time a voucher with Design Edition will be included with no additional cost." Is this licence time limited in any way, I.E. will I have to purchase a DE licence at some point in the future or will I be able to use the current version with this board forever? Is the voucher valid for a full licence or just a discount? Another question, if I purchase a Digilent board through a 3rd party reseller like Mouser electronics, do I still get the voucher? Thanks! regards, Vedran
  4. Hi, I'm a newbie trying to learn about the Genesys 2 board and would like to program the onboard OLED as an exercise. I'm following this tutorial. There is a prominent warning that says "Important! Make sure to turn off the OLED display before shutting down or reprogramming your board." Why? What will happen if I don't turn off the OLED display and simply turn off the power switch? Will it get damaged? This makes me very nervous to try my own programs since I will probably mess up at some point. Can someone reassure me that I won't do any permanent damage? Thanks!
  5. Hi everyone i am using genesys2 board. I want to test the board with simple code. but i meet a problem with clock, can you help me to fix it? thank this is code: and this is xdc the error in bitstream like this [DRC NSTD-1] Unspecified I/O Standard: 1 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to
  6. Hello, I'm designing a custom FMC board to use with my Genesys 2. Is there any informations about GTX and serdes pair length ? Thanks
  7. I need to use the IBERT IP core on a Genesys-2 FPGA board. I am using FMC-SMA board to convert FMC into SMA. In the clock settings I am using the external clock source from pin AD-11/12 of 200MHz. But the problem is I am unable to get any output as PLLs are not locked. I had followed the same steps with FMC board and all things where working fine. 1. Can I use the internal clock in the clock setting. (I tried but getting the INFO:- [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. ) 2. Do I n
  8. Hello! I am working on implementing the IBERT IP core on the Genesys2 dev board. I have purchased this daughter board to connect to the FMC, but I am unsure of how the pins relate to the SMA connectors. Has anyone used this daughter board before? I have emailed Hitech Global for documentation, but I have not received a response as of yet. Also, does anyone know if a guide such as this one exists for the Genesys2 board? I assume that the steps would be very similar since they both use the Kintex-7 FPGA. Thanks
  9. Just received a new Genesys 2 board. Flashed it and trying to boot the prebuilt version of linux from arian-sdk Programmed the board according to here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-programming-guide/start The board powers up fine, copies bbl & linux image from sdcard and then no tty output. Nothing at all. I built the sdcard using the prebuilt bbl.bin images from: https://github.com/pulp-platform/ariane-sdk/releases (I tried bbl.bin files from both 4.2 release and OpenPiton + 4.2, same result for both.) Following instr
  10. Hello, I am running Vivado 18.1 and would like to try to get the echo server running by following this demo. I understand that the demo hasn't been verified on Vivado 18.1, but nevertheless I would like to try it. The only problem is that my block diagram doesn't quite match what is displayed on the demo screen shots, even though I have double checked the steps to create it. Is there a bd tcl file available to recreate this diagram for the demo. If not, can a higher resolution picture of the completed diagram be posted?
  11. Hi I want to use a genesys2 FPGA with ADC from TI,so I download xdc file of Genesys 2 from GitHub to use FMC pin of Genesys 2 but I don't find the description of all pins especially those pins
  12. Hi all, Is the gerber file for the Genesys 2 board available to the public? Or can you tell me location of traces between FPGA/FMC? I see eight traces with meandres, are the traces for GTX? Thank you.
  13. Hi all, was Genesys 2 board tested for a maximum transceivers capability (10.3125 Gbps)? Thanks for reply. Tomas
  14. Hi all, We are a small startup looking for an pga development platform. We need a fast ADC/DAC FMC board and right now we're looking at the fmc163 from abaco https://www.abaco.com/products/fmc163-fpga-mezzanine-card. The board needs an FMC connector that conforms to the ANSI/VITA57.1 standard. I called Abaco and they confirmed it works with the Xilix KC705 kit https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html via this adapter https://dedicatedsystems.com.au/products/fmc700/ but couldn't confirm compatibility with the genesys2 board directly. I couldn't find any informati
  15. Hello everyone, I need suggestion about following topic: 1) I want to use an external oscillator 54 MHZ. And I want to take input this clock by FMC connector HA/LA pair (3.3 V) of genesys2 board. Is it will be ok? 2) The fixed oscillator 200 MHZ in Genesys2 is differential. I am producing my master clock for my design by MMCM. How can I have the minimum jitter? Any suggestion will be very helpful. Thank you Rappy Saha
  16. i am a student. my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification) i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that. but the instruction is always 0x00000000 !! (i used chipscope to detect the signal) (i used startupe2 to access CCLK) it seems like i didn't access the flash, can anyone help me? thanks a lot !! pls save me....
  17. Hi everybody I have a problem with the downloaded OOB design for Genesys 2: the DisplayPort seems to be properly configured, but the video does not appear. (It is not an issue related with the board, because the OOB stored on the flash of Genesys2 perform perfectly). I downloaded the design from the GIT (https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-user-demo/start), dated 2017 March 18. Another ZIP is available, dated today (2017 May 2), looking inside they seems equivalent. Both designs are the previous version of the OOB, updated to
  18. Dear all I prepared yesterday evening an SDK 2015.4 project, to be used with the bitfile, hdf and bmm generated by Vivado 2016.4. This way there is a discrepancy between HW and SW version, but if it works who care. Unfortunately, the elf behaves as the design recompiled under SDK 2016.4. Additionally the display link seems less stable, it continuates to disconnect and connect The connection is correct. MArco.
  19. To cap off the Differential PMOD Challenge Project I present a project that uses the HDMI interface. This is the Genesys2_DDR design with real clock capable pins, buffered IO, and a high speed connector over a 1 meter cable. Data transfer rate goes from under 57 MB/s to over 230 MB/s. And, we can double that with a bit more effort. If you've been following the Differential PMOD Challenge discussion then you'll want to look at this project. If you work for Digilent then please read on.... HDMI_DATA_PIPE_DEMO_Release1.zip
  20. Hi, I am using genesis 2 board for my ongoing project. For flash programming, I have followed this tutorial. But now I am using Microblaze that's why I need to use SDK. But, I don't know how store SDK project into flash. I followed the "Getting started with Microblaze". But, If I want to upload the whole project to the flash what should I do? So, when I power up the Genesys 2 and connect the UART port by terminal application (Teraterm), The program will boot up from the flash and display the "Hello world" on the terminal display. Any suggestion will be very helpful. Thanks.
  21. Are you interested in trying out a 10.8 Gbps 4-lane data interface on your Genesys2 board? Try spending some time in Transceiver Boot Camp. You won't be disappointed. TransceiverBootcamp.zip
  22. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy
  23. I am working on Genesys 2 board for a while using Vivado 16.1 on Windows 10. It worked fine until yesterday. After rebooting my PC SDK/ Vivado is not detecting FPGA. I am not what has gone wrong suddenly. Please Help D
  24. Hi, I am using block memory generator 8.3 in vivado16.2. I am using to store my image sensor data. The resolution of the sensor is 1280*1024(=1310720). And each pixel contains 16-bit. Parameters I am using: Interface type: Native, Memory type: Simple Dual port RAM. PORT A is used for writing the pixels into the memory block. PORT B is used for reading out. Port A Width: 16 Range: 1 to 4608 bits (as each pixel has 16 bit) Port A Depth: 1310720 Range: 2 to 1048576 ( but this value exceed the range) So, I am thinking to write two pixels into the memory at a time so that
  25. Hi, I am very new at field of FPGA. Now I am working Genesys2. I have to control DDR3 memory. I find some examples in Digilent site for DDR3 using microblaze processor. But, in my case I don't have to use microblaze processor. I have to send some fixed value through the DDR3 memory like 8-bit data (X'FF') i.e. I will write that data into the Genesys2 DDR3 memory and readout the data from the memory. I already go through Xilinx manual ug_586 . But still it is not clear to me how to start coding for the DDR3 memory. My questions are: 1) Is it possible to have example code without using