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Found 14 results

  1. Zygot goes back to the future to transfer data between two FPGA boards at 600 MB/s. Along the way he has a debugging adventure, learns ( AGAIN!!! ) why free stuff rarely is free and remembers when Digilent made FPGA boards that were great for development projects. This is a nice project for beginners or old hands to read through even if you don't have the hardware. CAUTION!!! You must read through the README text file before trying to replicate this project in hardware. Release 2 fixes some bad commentary in the source files and improves the behaviour of the UART transmitter FastDataInferface_R2.zip
  2. ee_engineer

    Digilent Genesys LVPECL Differential Clock

    Hello there, I am working with a Digilent Genesys Virtex-5 Development Board and want to implement an LVPECL output clock. The Genesys 1 board has a Virtex-5, which supports LVPECL, but I cannot find the LVPECL output on the Genesys 1? Looking through Genesys 1 board schematics, I could not find LVPECL_25 outputs as seen in the Virtex-5 FPGA User Guide.
  3. Bruce

    Genesys Encrytpion

    Has anyone been able to load an encrypted mcs file on the Virtex 5 based Gensys? I can encrypt the bit file and load it directly and the board boots (of course once I load the encryption key.) However, when I load the MCS file the board doesn't boot, and a scan of the device status in Impact shows CRC error.
  4. Hello guys, I have read in the Genesys board's reference manual that a reference design that displays color bars on the screen, I already checked the resource center but I can't find it, could you please help me peace, Taki Eddine
  5. Hi guys, Actually this is my first post in this forum, could you please provide me with some guidlines of how to implement HDMI controller on genesys board starting from the Atlys's one ? peace,
  6. Hello, I want to feed video from my smartphone camera to Genesys and want to display the video on the PC. I don't know how to interface. How should I connect my smartphone camera with Genesys board? I also want to do the same thing with Nexys 4 DDR board. Any kind of information will be helpful. Thank You.
  7. emanueay

    Genesys dev board - PCB design

    Hi- I'm currently designing an interface board to the VHDCI connectors provided on the Genesys dev board (SKU 410-138). The schematic design doc is avalable on the resource link to the Genesys board, however not the PCB design doc. Where can I get a copy (i.e. PDF format) of the Altium PCB gerber files for this dev board? It will help me by providing guidance to design a reliable PCB with proper signal integrity by following similar layout/routing strategies. Additionally, the Genesys datasheet should have included application notes with PCB recommendations. Cheers, Emanuel
  8. emanueay

    LVDS characteristic impedance

    Greetings, I need to know what is the output characteristic impedance of the VHDC connectors on the Genesys Virtex 5 FPGA Develpment Board. The datasheet only says they are impedance-controlled matched pairs and the schematic does not have this info. Some online forums said SCSI is defined by ANSI X3.13, the nominal diff cable impedance is 122 Ohms and I want to check if my board IO is consistent with this standard or not. I need to design a mating board to convert high speed differential signals into single ended, and signal integrity is a big deal. Thanks in advance, Emanuel
  9. agdiaz1

    Gigabit Ethernet

    Hello, I am a student of electrical engineering, and I am using a Genesys board with a Virtex-5 to try to send information and Gigabit Ethernet speed. Previously I was working with the Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Core at MII speed and managed to learn from the example design provided (the address swap module). However, the example design that comes with the Core at GMII speed comes with more clock requirements that are difficult to implement. How can manage the constraints for all the clocks that are needed to make this example to work? Can somebody help me with making the example design work?.
  10. zygot

    Genesys DDR with ISE 14.7

    I need to use the Genesys DDR2 SODIMM connected to logic ( no soft processor ) using the ISE flow instead of XPS. Has anyone at Digilent a working project similar to the DDR test available for the Atlys board? Curiously, the MIG tool doe not let me assign the correct pin to the ddr_wen signal.
  11. Greetings, New user to the forum, hope I can contribute some in the not so distant future. I am here by the recommendation of Digilent technical support. I am the new owner of a suspected malfunctioning Dev board (Genesys / Xilinx ) . Perhaps someone out there has some on hands experience with this particular product? I am having difficulty getting a power good indication (LD8) when I apply the required 5V supply. For a short time I have been exploring the Adept interface in an attempt to communicate with the board and when using the Power meter I notice the various voltages along with respected currents seem to be okay except the 2.5 V output indicates around 2 Volts and shows around -8 to -10 mA current. To me, this suggest no 2.5 V supply being generated by the switch mode power supply, are there any suggestions what to look for? So far, I have not had much success with email support in this matter. I really would like to get upto speed so I can contribute to the FPGA development community. Thank you in advance, J.L. Moon
  12. Hi , Myself trying to make Ethernet link up (without lwip) on Genesys Virtex5 Board. I generated EMAC0 wrapper with loop back from Xilinx Code Generator , modified ucf for board schematic. Reeceive link is working fine , i.e my board is able to receive I Gbps packets from PC and in chipscope pro , I could see packets loop backed on the TXD lines and PHY TX led is blinking but no packet is reaching PC . The problem , I assume may be the TXD line delays and PHY not getting proper data from FPGA . I don't have visibility to the TXD lines at PHY side . I tried out a couple of things thinking that the PHY may not be getting window to sample data properly. 1) GTXCLK is shifted at 90,180,260 PHASES using DCM ..No luck :-( 2) Drive strength of I/O reduced which can reduce EMI interference 3) Slew rate changed Nothing worked out ..So please help me out with some suggestions. Thanks & Regards, Supriya
  13. Holly87

    Genesys Board + Impact Xilinx Tool

    Hi everybody, I have just bought a Genesys Board (Virtex 5 FPGA) and I want to use the Xilinx iMPACT Tool to program it through the dedicated USB port. Is there any documentation available about step-by-step configuration and programming of the Genesys with the iMPACT Tool, for beginners? Thank you! Holly87
  14. Alex

    Vmod CAM Atlys demo port to Genesys

    If I want to port the current Vmod CAM Atlys Demo to Genesys. Do I only need to change the UCF and target device?