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Found 3 results

  1. I am trying to follow the 'Getting Started with IP Integrator' tutorial provided by Digilent with the Genesys2 FPGA boards, and despite it seeming like a simple tutorial, I can't get it working at all. It looks like the on-board LEDs aren't being routed to the correct pins once I run the implementations. While following the tutorial, adding the IP, and configuring it works well. When installing Vivado on my Windows 10 machine, I downloaded the board files from Digilent following their tutorial as well. I can see the Genesys2 board upon creating the project, so I don't see the issues coming from there. Aside from following that tutorial to a T, I also changed the clock IO Standards in the part0_pins board file to 'LVDS' as implementation was not operating properly without that - complaining about the wrong IO standard. The change has been attached to this post. The errors I get from the messages window have also been attached to this post, and appear when the bitstream generation fails. After reading the messages and 'googling' around, users said that those errors arise when pins aren't being fixed to a package pin. I then searched around the implementation, and notice that there's a bank called led_8bits_tri_i, in the I/O ports page, that are being suspiciously mapped as inputs, all to the correct package pins. I expect the error messages are coming from the led_8bits_tri_o ports, which aren't being mapped at all. I'm not sure how to remap them, as I've tried superseding the board files with XDC files, yet the mapping issues persist. If anyone has experienced this before, or could provide some insight, that would be greatly appreciated, Thanks, Justen part0_pins.xml
  2. Hello: I am unable to get Ethernet interface to work on Genesys-2 in my design which is migrated from a Xilinx board. I have a Microblaze based design that I am trying to port to Genesys-2 Board. This design is working on Xilinx KC705 evaluation board which uses the same Kintex-7 FPGA as Genesys-2. On this design I have Ethernet interface, DDR3 Interface and some other peripherals. We are using Linux for this design. This design was originally developed by another company and was used for evaluating their chip. It was developed on Xilinx evaluation board KC705. This company does not support any other evaluation board. I am hoping to get some help from forum experts to bring-up this design. For this design on Xilinx KC705 board after power up, downloading the bit file and running the SW from *.elf file we can open a PUTTY terminal and issue 'ifconfig' command to check whether the ethernet interface is up and which IP address it got. This works for Xilinx board. But the same does not work for Genesys-2 board, I can issue 'ifconfig' command but I don't see the ethernet interface active. I had looked for pinout differences and made changes accordingly. When I described the symptoms to the original authors of the design they said that because the PHY is different between the two boards I have to update the device tree. Below is the device tree from Xilinx KC705 design. Ethernet Device Tree axi_ethernet: ethernet@40e00000 { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&axi_intc>; interrupts = <1 0>; local-mac-address = [00 0a 35 00 00 02]; phy-handle = <&phy0>; reg = <0x40e00000 0x2000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,select-xpm = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; PHY on Xilinx KC705 board is Marvell 88e1111. PHY on Genesys-2 is RealTek RTL8211E. The original authors of the design had suggested that at a minimum the line "reg = <7>;' should be changed for Genesys-2. My questions on the forum are below. 1) How should I modify the device tree for Ethernet for Genesys-2 board? 2) Does it seem that just changing the device tree for Ethernet will fix our issue? 3) Any suggestions on how to debug this issue? Thank you so much. Best regards,
  3. I want to buy a Kintex-7 board, it seems Genesys-2 is a good choice. But I want to check the resource before ordering it, is the schematic of Genesys-2 available? Is there a list of reference designs for this board? thanks!