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Found 13 results

  1. Hi, Could anyone share their experience with Genesys 2 and Vivado voucher license? The Genesys 2 Vivado license (acquired via voucher) is node and board locked. I wonder how restrictive board lock is: Can I generate the bitstream on one computer (the "node" license is locked to) and program on another? Does the the board need to be connected to the "node" for Viviado to work? (or the lock is just put in the bitstream?) If I have two Genesys 2 boards, do I have to have two copies of Vivado installed? Thanks, Peter
  2. Hello, I'm a student and I'm designing a project which transmits data from a dual ADC board (ADS4249) over optical fiber and then reconstruct it to Analog signal using DAC3283 DAC evaluation board by TI. Both of those evaluation boards got a FMC to DAC/ADC adapter: http://www.ti.com/tool/FMC-DAC-ADAPTER http://www.ti.com/tool/fmc-adc-adapter TI claims that it is for Xilinx FNC connector. I wonder if anyone tried to connect those boards to Digilent Genesys 2 evaluation board FMC connector? Are they pin compatible? Is there any source code? TI provide source code for Altera FPGAs only. The other question is about interfacing to SFP+ optics: I would like to interface a SFP+ cage to every board. There are no dedicated connectors and I cannot use the FMC connector because the ADC or DAC would be connected to it. There are many SFP+ boards with SMA connectors for the 10.3 GHz signals and simple 2 row connectors for the I2C interface. Is there any place in the Digilent Genesys 2 board to connect 2 cables for the 10.3 signals? Please consider the fact that the FMC connector would be probably occupied by the ADC or DAC card and I cannot use FMC to SFP boards.. If those lines are already connected to other function on this board - like USB or VGA etc. then I don't mind disconnecting them. I see that the FPGA has "2FF" speed grade so it has transceivers which support 10.3GHz signals. As for the I2C signals needed for programming the SFP - Can I use standard GPIO lines? From where can I connect them? I would appreciate your detailed response. SagiFTW
  3. Hi There is a way to download the original Vivado 2015.4 project? Thanks in advance, Marco.
  4. Hi guys Sorry if I'm back i compiled the OOB design downloaded from your site, the ZIP file (dated 2 may 2017),,,,, the result is that Displayport continuates to be correctly trained and configured, but screen does not display. Additionally, in this version HDMI does not work too. At this point I suspect a problem in RTL (BD, constraints) sources. May you check the functionality of your distribution on a Genesys2 Board? Thanks in advance. P.S. Obviousy with other designs HDMI works fine, and with project available in flash displayport too,
  5. I'm working on a simple HDMI capture and transmission to PC using DPTI. My HDMI decoder is modified code from @hamster and DPTI code is from Digilent Adept SDK package. I have tested both of them on their own but when I try implement them together I get the following error. When I add the sugested line to my constraints then I get this error. And adding this line gives me that when generating a bitstream. I have tried adding BUF elements to the HDMI design but then SerDes and TMDS decoder stop working.
  6. Hi, I am trying to generate a project from Digilent's GitHub. I followed this following manual: 1) https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-user-demo/start 2) https://reference.digilentinc.com/learn/software/tutorials/vivado-projects-from-digilent-github/start?redirect=1id=vivado/github so, When I execute the command "source ./create_project.tcl" according to the manual link 2, it gives me following error messages: "ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.2> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.2>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script. ERROR: [BD 5-229] Please open or create a block design first. ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors." So, how can I solve the problem? Do I need to download Vivado 2015.4 or I can do it on the Vivado 2016.2? Any suggestion will be appreciated. Thanks.
  7. Hello Programmers who love programming down to the bare copper! I've been teaching myself Verilog using Xilinx ISE Design Suite on a little Spartan FPGA for my lifes's work project over at qbitrex.com. It a Quantum Computing simulation. I found the logic gate I'm going to simulate a qubit its a clocked JK Flop that preserves both Q and NotQ to comply with the reversible computing spec of quantum computing. Next major step is transmute the electronic into photonic and let it interfere in a beam splitter on a bigger FPGA. Before that however I need to drive four (4) OLED Arrays Alice and Bob Transmitter and Receivers. So my question is can the High Pin count FMC Connector on the Genesys 2 be used to signal the 30 pin parallel digital signals for each 128x128 OLED array which are not FMC connector types?
  8. We refer to "PC - FPGA Data Transfer (DPTI/DSPI)" function detailed into the Genesys User Manual The IC20-FT2232 is clearly visible on the Genesys 2 Board but is undocumented in board schematic, UCF connection are missing, In this approach This function is fully unusable. Question 1: Can Anybody provide details on the IC20 Gost connectivity...!!!!. Question 2: Is This port compatible with ADEPT SDK?? Luigi
  9. I unable to resolve the issue please kindly fix this if anyone had experience in this..... img.vhd mat_ply.vhd bram1.coe
  10. Is there documentation on how to write a controller to read and write data to a USB mass storage device formatted with FAT 32 file system on the Genesys 2 board? If not what specifications, datasheets etc do I need to study in order to develop such a controller.
  11. Hi, Is it possible to program the Genesys 2 board using the xc3sprog tool? I've tried with many different cable types with no success. Thanks.
  12. UCF/XCF data of of SDRAM on board of Genesys 2 isn't inside the provided XDC file (Pin allocation of SDRAM is missing). Anyway Connectivity can be solved manually recovering pin names and functions from the provided board schematic. Should be better to fill these data inside XDC reference file.
  13. molbojs

    Genesys 2, AD9739A FMC

    Hi, I have the Genesys 2 FPGA with the AD9739A connected at the FMC port. According to the datasheet the input-pins for the AD9739A are differential. The corresponding pins at the Genesys are the fmc_la-pins which are single ended. How are these pins suppose to be configured to work with the AD9739A? I have tried to use the reference design from Analog devices but i seems to be out of date. Any suggestions on how I should solve this problem? //Daniel