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Found 16 results

  1. Dear All, I was able to port the camera design to Genesys 2 board. I see this Visible Border Line as mentioned in Zybo Z7 demo description. Is there a solution for this problem already available? I use following IP blocks: MIPI_D_PHY_RX (1.3) -> MIPI CSI-2 Receiver (1.1) -> AXI_BayerToRGB (1.0) -> AXI_GammaCorrection_0 (1.0) -> axi_vdma Thank you Linas
  2. Tom G

    Genesys 2 HDMI demo

    Does anyone have the Digilent HDMI demo running on the most recent Xilinx IP cores / Vivado 2019.2? Upgrading the IP cores (necessary because I don't have a license to the old ones) seems to result in the bitstream generation failing and a ton of error messages that I can't see how to resolve. Any help much appreciated.
  3. Hello, I'm a student and I'm designing a project which transmits data from a dual ADC board (ADS4249) over optical fiber and then reconstruct it to Analog signal using DAC3283 DAC evaluation board by TI. Both of those evaluation boards got a FMC to DAC/ADC adapter: TI claims that it is for Xilinx FNC connector. I wonder if anyone tried to connect those boards to Digilent Genesys 2 evaluation board FMC connector? Are they pin compatible? Is there any source code? TI provide source code for Altera FPGAs
  4. Dear All, what is the situation with reference design of Genesys 2 board and Pcam 5C camera? I see, that Genesys 2 board supports FMC Pcam Adapter and up to 4 cameras. So is this reference design available or user must port it by himself from another Digilent board? Genesys 2 is great board with plenty video connectors for video applications otherwise. Linas
  5. Hi, Could anyone share their experience with Genesys 2 and Vivado voucher license? The Genesys 2 Vivado license (acquired via voucher) is node and board locked. I wonder how restrictive board lock is: Can I generate the bitstream on one computer (the "node" license is locked to) and program on another? Does the the board need to be connected to the "node" for Viviado to work? (or the lock is just put in the bitstream?) If I have two Genesys 2 boards, do I have to have two copies of Vivado installed? Thanks, Peter
  6. Hi There is a way to download the original Vivado 2015.4 project? Thanks in advance, Marco.
  7. Hi guys Sorry if I'm back i compiled the OOB design downloaded from your site, the ZIP file (dated 2 may 2017),,,,, the result is that Displayport continuates to be correctly trained and configured, but screen does not display. Additionally, in this version HDMI does not work too. At this point I suspect a problem in RTL (BD, constraints) sources. May you check the functionality of your distribution on a Genesys2 Board? Thanks in advance. P.S. Obviousy with other designs HDMI works fine, and with project available in flash displayport too,
  8. I'm working on a simple HDMI capture and transmission to PC using DPTI. My HDMI decoder is modified code from @hamster and DPTI code is from Digilent Adept SDK package. I have tested both of them on their own but when I try implement them together I get the following error. When I add the sugested line to my constraints then I get this error. And adding this line gives me that when generating a bitstream. I have tried adding BUF elements to the HDMI design but then SerDes and TMDS decoder stop working.
  9. Hi, I am trying to generate a project from Digilent's GitHub. I followed this following manual: 1) 2) so, When I execute the command "source ./create_project.tcl" according to the manual link 2, it gives me following error messages: "ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.2> of Vivado. Please run
  10. Hello Programmers who love programming down to the bare copper! I've been teaching myself Verilog using Xilinx ISE Design Suite on a little Spartan FPGA for my lifes's work project over at It a Quantum Computing simulation. I found the logic gate I'm going to simulate a qubit its a clocked JK Flop that preserves both Q and NotQ to comply with the reversible computing spec of quantum computing. Next major step is transmute the electronic into photonic and let it interfere in a beam splitter on a bigger FPGA. Before that however I need to drive four (4) OLED
  11. We refer to "PC - FPGA Data Transfer (DPTI/DSPI)" function detailed into the Genesys User Manual The IC20-FT2232 is clearly visible on the Genesys 2 Board but is undocumented in board schematic, UCF connection are missing, In this approach This function is fully unusable. Question 1: Can Anybody provide details on the IC20 Gost connectivity...!!!!. Question 2: Is This port compatible with ADEPT SDK?? Luigi
  12. I unable to resolve the issue please kindly fix this if anyone had experience in this..... img.vhd mat_ply.vhd bram1.coe
  13. Is there documentation on how to write a controller to read and write data to a USB mass storage device formatted with FAT 32 file system on the Genesys 2 board? If not what specifications, datasheets etc do I need to study in order to develop such a controller.
  14. Hi, Is it possible to program the Genesys 2 board using the xc3sprog tool? I've tried with many different cable types with no success. Thanks.
  15. UCF/XCF data of of SDRAM on board of Genesys 2 isn't inside the provided XDC file (Pin allocation of SDRAM is missing). Anyway Connectivity can be solved manually recovering pin names and functions from the provided board schematic. Should be better to fill these data inside XDC reference file.
  16. Hi, I have the Genesys 2 FPGA with the AD9739A connected at the FMC port. According to the datasheet the input-pins for the AD9739A are differential. The corresponding pins at the Genesys are the fmc_la-pins which are single ended. How are these pins suppose to be configured to work with the AD9739A? I have tried to use the reference design from Analog devices but i seems to be out of date. Any suggestions on how I should solve this problem? //Daniel