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Found 191 results

  1. Matrix reception module in vhdl

    Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab). Thank you for your attention
  2. Creating a 25 Mhz clock on the Basys 3

    Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I want to call it I just make a instance of this class. In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached } So my questions are : Is this the proper way to set up a clock using Vivado and the Basys3 Board?In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties] I can only find clocks as high as 66 MhzAnd just some basic ones Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ? Thanks Forum .
  3. I am trying to load my program to a Block RAM using Data2mem, after the bitfile is generated. Here are the steps: I have generated a BLOCK RAM as single port ROM with 32 bit-width and 16384 bit-depth. Then translated the design without any BMM file and looked at the PlanAhead tool to see which BRAM are used and which ramloop is assigned. There are 15 ramloop lines. There are 14 PRIM36 primitives and 1 PRIM18 primitive as shown below: BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP **(RAMB18)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP **(RAMB36_EXP)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) I wrote the following .BMM file for address the ROM from 0x0000 to 0xFFFF. and add it to the xilinx project. ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff] BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; END_ADDRESS_SPACE; But when I tried to compile it again it gives me the error: ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE 'pr_mem1'. Can you please help me out where the error is occurring? Is ramloop[xx] correctly used?
  4. Zybo: Access the LD_MIO LED from the FPGA

    Hi, I have a Zybo board and am using Vivado 2017.2. I have successfully written a number of VHDL modules allowing me to access the boards push-buttons, LEDs and slide switches using only the PL part of the device. I wondered if it was all possible to drive the LD_MIO LED from the FPGA? From my understanding it should be possible using the EMIO but have not been able to find an example or tutorial that shows how it is done. Regards FarmerJo
  5. Non-clocked synchronous circuits

    I was reading Dan Gisselquest's blog (aka @D@n), in particular, this specific part of the one that goes into some detail about the ALU for his ZipCPU: https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/cpuops.v#L317-L343 always @(posedge i_clk) if (i_ce) begin c <= 1'b0; casez(i_op) 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB 4'b0001: o_c <= i_a & i_b; // BTST/And 4'b0010:{c,o_c } <= i_a + i_b; // Add 4'b0011: o_c <= i_a | i_b; // Or 4'b0100: o_c <= i_a ^ i_b; // Xor 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR 4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL 4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR 4'b1000: o_c <= w_brev_result; // BREV 4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO 4'b1010: o_c <= mpy_result[63:32]; // MPYHU 4'b1011: o_c <= mpy_result[63:32]; // MPYHS 4'b1100: o_c <= mpy_result[31:0]; // MPY default: o_c <= i_b; // MOV, LDI endcase end else // if (mpydone) // set the carry based upon a multiply result o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; Dan makes the comment: "Each of the blocks in this figure takes up logic when implemented within hardware. As a result, even if i_op requests that the two values be subtracted, all of the other operations (addition, and, or, xor, etc.) will still be calculated. These other results, though, are just ignored. Thus, on the final clock of the ALU, all of the operations have been calculated, but only the result of the selected operation is stored into the output register." (bold emphasis mine) I found this a very interesting comment. Dan shows how there is effectively a multiplexer based on the opcode on the output of each of the logic chains. It strikes me that this is quite a waste of power, in general, so I wondered how, or even if it is possible to do things differently. Using one of the ZipCPU ops as an example, could one reliably implement something like the following? always @(posedge i_clk) if (i_ce) begin do_cmp_sub_op <= (i_op == 4'b0000) ? 1'b1 : 1'b0; ... rest of the op codes go here ... always @(posedge do_cmp_sub_op) begin {c,o_c } <= {1'b0,i_a}-{1'b0,i_b}; do_cmp_sub_op <= 1'b0; end There are many reasons why this is not something you would do in real life in a CPU, among other downsides it would have the effect of adding extra logic and an additional (at least) 2-clock latency right as the rising edge of the various do_xxxx registers would be one cycle behind, plus you'd need another cycle to turn the clock off so that you could catch a rising edge. So clearly this isn't something one would do for CPU ops that only take 1 cycle. 1) What are the various ways to only have some of the gates / logic working in a system while most of it is quiescent and only run when needed? 2) Does an if statement have the same logic as the case in this respect, i.e. does the logic for i_ce is 1, and i_ce is 0, also both get run but discarded on the input side of a multiplexer as well? 3) What are the options and tradeoffs involved in deciding what to use as the triggers for logic?
  6. AXI DMA

    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. https://github.com/mstuehn/dma_proxy Any help is appreciates Best regards,
  7. Hi all, May I humbly ask the experts in this forum if you already tried to implement AT commands into FPGA to make the cellular module works and be able to use the internet inside the FPGA. Ours, want to implement the cellular module via RS 232 interface into the pmod zedboard. Hoping for some guidance on how to go through it. Thank you in advance. Best regards, Glenn
  8. Petalinux Kernel module

    Hi I want to transfer data from PL to PS via DMA. I am using zedboard. I am using petalinux in the PS. i have created a module for the DMA called "axidma". i have a header file in the module named axidma.h where i have defined some macros. axidma.h and axidma.c are in the same directory. Now i want to use those macros in user space applicatiion but i cannot access them. I know it is possible by changing the makefile of the module but i am not an expert in makefiles so i dont know how to do that. Any help will be appreciated
  9. implementation of a filter in an FPGA

    Good afternoon everyone, I was wondering if someone implements a filter in an FPGA in VHDL language, but that was designed and generated by the FILTER DESIGN HDL CODER tool (Matlab). To help me with some doubts. Thanks
  10. Hi there I am selling my Zinq-Z1 board ( zynq 7020 ) She is "as new". I put Arty Z7 in the title because these two board are so similar (not the same colour of pcb, and the Pynq has one thing more: a mic) mine is a pynq. My price is 99€ plus shipment , you can find easily on ebay my announce, there are some photos, I also sell on ebay my Spartan 6 board (papilio duo and computing shield) Thx & Regards B.
  11. uart receiving module for 16 or more bits

    Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  12. CMOD A7 System Generator

    Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  13. To know parts of processores

    I want to list of small parts of processor and it's size like adder ,comparator ,etc ,please help me with it .
  14. Hello everyone and nice to meet you. I am a user of Zybo and until today everything was fine. But today I tried to use this board with a BLDC motor control board and something went wrong... The motor was not connected to the board, but battery was. The goal was to check correct operation of the MOSFETs (by PWM) at the control board and check it with oscilloscope. When I didn't see what I wanted to see, I turned Zybo off and back on, but it didn't turn on. The symptoms are as follow: - Short circuit between VCC3V3 and GND; - All other voltages are not short circuited; - The voltage converter seems ok too. Unsoldered R259 (zero Ohm resistor between converter's output and other circuit), but short circuit still remains. - Resistance of the pin used for PWM (to control MOSFET hi-driver) is infinite; - Zener diode connected to this pin changed its internal resistance as well (unsoldered it but it didn't change anything); - All other PMOD pins have finite resistance ~600 kOhm; - The PWM pin was surely connected to an input pin of the MOSFET driver. Is there any way to check if it is a permanent internal damage of FPGA without unsoldering it or not? I am pretty sure it happened because of that PWM pin but don't know why exactly. It might happen because of static discharge (though Zener diode should protect against it) or incorrect connection somewhere else by accident. Thank you for your time. Hope to get some hints soon. Regards,
  15. http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/ Got it under student edition from the university for a course. Used for 4 months only.
  16. Hi, I am using windows OS and want to know the use of USB port on Zybo board. I have no idea how it works. Can I able to implement using verilog or I must need Zynq processor? I appreciate if anyone have sample project which will describe the use of USB port using zybo board on windows OS. BR ALI
  17. FPGA learning kit needed

    Hi, My name is Yaniv and i just finished my Electrical & Computer engineering degree. I want to be a FPGA engineer and i need to get a little experience in the next few months (all jobs require 3 + years experience in my country). It would be really nice if you guys could recommend me about FPGA learning kit. I know its digilent site but every FPGA learning kit will be welcomed:) I get the basic point what it is but i dont really understand which one would be better in terms of course material of the internet! Thanks!
  18. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  19. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  20. motor controller with BASYS3 and UART

    Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  21. Cmod A7 Clocking

    The schematic diagram for the Cmod A7 shows a clock with part number ASEM1-100.000MHZ-LC-T, which is a 100MHz clock. However when I look at the actual clock component it says it's 12MHz chip, which I confirmed by scoping the output. Is there any way to get a 100MHz clock signal out of this board?
  22. Dividing by 10....

    Tonight I discovered that this is a fast way to divide by 10 unsigned div10(unsigned x) { #ifdef REF /* Implement 32-bit division using divide */ return x/10; #else return (x * 0xCCCCCCCDLLU)>>35; #endif } Just wanted to post it here in case it becomes of use to somebody. A variant It could most likely be used with a DSP48 block to divide shorter (20 or 23 bit) binary numbers with much less resources and latency than a 10-bit binary divider.
  23. arty Z& petalinux BSP Error

    Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here https://github.com/Digilent/petalinux-bsps/wiki/Quick-Start-Guide-for-Arty-Z7. But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  24. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  25. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you