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  1. Hi guys, I bought my genesys 2 last october, and now when I turn it on, the out of box demo would only succeeds a fraction of the time. More over, previously verified bitstream would only work once after programming with jtag several times. I suspect the fpga chip is a defect. How do I use my warranty? Thanks
  2. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (ju
  3. Hi, I am using Zybo Z720 and Pmod ESP32 to explore on IoT control. I used several AT commands like "AT+CWMODE", "AT+CWJAP", "AT+CIPSTART", "AT+CIPSEND" and "GET <links>" to receive the last entry data from the Thingspeak. Here is the response I received from the Vitis Serial Terminal: Now, I want to make use of this data from +IPD response and control the GPIO and relay (relay connected to the GPIO pin). I know Arduino has sth like Serial.find() function and help me with extracting serial terminal's IPD response. I just wonder Xilinx Vitis has the same thing a
  4. Previously I have asked this question in the forum, however, my explanation was not so clear and may result in confusion. Hence, I decided to rephrase my question in this new post. Currently, I have been researching on how to allow my Zybo z720 board to receive data from Thingspeak channel through using Pmod ESP32 and control the status of the LED according to the data of Thingspeak. I have already known how to send the data (collected from ALS, AQS and HYGRO) from the zybo board to Thingspeak by using the AT command. I will show the code below. void receiveData(XTime time){ X
  5. Hi, I am using Pmod ESP32 and figure out the possibilities to receive data from Thingspeak. Based on my research, I found this link may help me to get Thingspeak data via using AT command. The link is here: Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board ( This picture (picture is from the link above) tells me what AT command I should use for receiving data from Thingspeak Cloud.
  6. Hi, I have been trying to use the zybo board timer interrupt functions to control my water pump while running other program, kind of like multitasking. The program goes like this, when the my other programs are running in the while(true) loop (running forever), the water pump will turn on for 12 hours and turn off for 12 hours. Before jumping into actual program, I made some simple testing. While the Pmod HYGRO is getting value, the led 4bits will have a loop of turning on for 100s and turning off 100s (like led toggling) Here is what I have tried with built-in led:
  7. Hi, everyone here. Now, I have tried with my Pmod AD1. I used the demo code provided by the Digilent, but the value shown in the Vitis Serial Terminal is different from the value I have seen in the multimeter. For example, when I insert my sensor A into the channel A0, the value shown in 2.56. The value shown in the multimeter is 2.9V. When I insert my sensor B into the channel A1, the value shown in the Vitis Serial Terminal is 1.08. The value shown in the multimeter is about 2.1V. When the sensor induced voltage exceeds 1.8V, the AD1 value returns back to 0. I thi
  8. Hi to everyone. I have successfully tried to use Pmod ESP32 to upload the other Pmod sensors data into the Thingspeak and used GPIO inside the zybo board to control the LED when some Pmod sensor value is too high or too low. Now, my supervisor asked me and my team to do IoT control. For example, an user pressed the button in the webpage or mobile app, the LED which connected to zybo board can turn on or turn off. My teammate now can send the 1 or 0 data to Thingspeak. Now, I want to use my Zybo baord to receive the Thingspeak data that my teammate has made. I have been searching some tuto
  9. hi, I have been facing issue and I want to figure out what type of reasons can cause it? Connection issue? Or sth else? For installing my program into the zybo board, it sometimes works while sometimes pop up this error message. Like intermittently working. Here are some error message: targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351AD668FA" && level==0} -index 1 fpga -file C:/Users/lukel/workspace8/test_3/_ide/bitstream/design_7_wrapper.bit targets -set -nocase -filter {name =~"APU*"} loadhw -hw C:/Users/lukel/workspace8/design_7_wrapper/export/
  10. Greetings, It is my first time here so I apologise for my mistakes, I started a new project where I am using Nexys 3 board with a Pmod GPS module. I found a UART receiver/transmitter on the internet I wanted to test it out. So I connected the receiver to the USB UART Rx pin, in order to send from Serial COM data and then transmit back to the Serial COM the data I have sent. When I am sending a character from the serial, I receive the same character from the UART transmitter so I think that both of the components work fine. When I am sending the character A, I receive back the character A
  11. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not requi
  12. Hello all, I am using ZC-706 zynq board as slave and atmega128 microcontroller as master. I want to do spi communication between them. For testing i am just transmitting 1 byte of data which is transmitting successfully from the master side. For FPGA slave i am using AXI quad spi IP core which is configured in slave mode. Please find the below block diagram design for same. From the PS side i am using the below SPI driver example which is mentioned below. /***************************** Include Files *********************************/ #include "xparamete
  13. For my project, I was asked to use the xadc portion of the zybo board to read the data from the DFRobot Gravity Analog Electrical Conductivity (EC) Sensor. The link of the sensor is here: Just to give a summary on this product, it has the supply voltage of 3V to 5V and output voltage of 0V to 3.4V. I have asked this question before, maybe due to the unclarity of the question, nobody has answered me. The link is here: I have been trying to learn the basics of xadc
  14. I am currently doing the vertical farming project. And I want to put my Pmod HYGRO and Pmod AQS sensor into the same port JC. I have tried to put my Pmod HYGRO and Pmod AQS into different Pmod ports successfully. Now, I just want to combine these two sensors into one port. For example, for port JC. I want the top layer of the port connect to Pmod AQS and the bottom layer of the port to the Pmod HYGRO. So what is my first step to do when comes to vivado block design and how am I going to write my Cpp code into Vitis IDE? I did some primary research on this topic before. I may n
  15. Dear all Please help in accessing ethernet port of Atlys FPGA board. Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it. please reply if anybody has done that. -- Gopal krishna
  16. Hello sir We purchased "Arty-Z7-20" a few weeks ago. We are trying to boot a project using the petalinux. We have followed the manual given in the below links. But the Arty-Z7-20 board didn't get booted via jtag or SD card. We have also followed steps provided on belowed github, but it won't work.. https://git
  17. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some
  18. Hi, i also Facing the same issue.. I'm setting up the Spartan 3E system using VM( VirtualBox -Win7 IE8) with installed with ISE 14.7 on my WIN 10 PC. the USB connection showed in Device Manager is Xilinx USE Cable, but when I run the IMPACT to program the FPGA it show the error below: Error: GUI --- Auto connect to cable... INFO:iMPACT - Digilent Plugin: Plugin Version: 2.5.2 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz re
  19. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  20. Hello everyone, So I own a Basys 2 board with spartan 3E FPGA and I am using ISE Design Suite 14.5. I want to create a VGA output with 800x600 resolution and 40Mhz clock so it will have 60Hz refresh rate. I am writing the code in verilog. I have entered exact numbers for horizontal counter, vertical counter, hsync and vsync that are required for operation stated above. However, I am unable to output the VGA signal. I am using two DCMs that can be generated in the ISE design suite, I am using first DCM to multiply 50MHz clk to 100Mhz and then I am using second DCM to divide 100Mh
  21. Hi, I am running acceptance test on NetFPGA sume and I have done all settings in Ubuntu. Board is attached to the PC and PC is recognizing that. Now when I run acceptance test it doesn't generate bitfiles and eventually it say that elf file of acceptancettest.elf is missing. I wanted to ask how can I solve it? Please inform Thank you
  22. Dear Team, We are using CMODA7 for one of our project. Unfortunately the Switching regulator got damaged.We are planning to change the swicthing regulator and it's associated components. Could you please share the BOM and placement files. Regards HARI
  23. Hi, I am using windows OS and want to know the use of USB port on Zybo board. I have no idea how it works. Can I able to implement using verilog or I must need Zynq processor? I appreciate if anyone have sample project which will describe the use of USB port using zybo board on windows OS. BR ALI
  24. Hi, I have Basys 3 for SPI slave and it supports 3.3 PMOD IO but I have 1.8V SPI Master So I need to have a way to use 1.8V PMOD. I went through the forum and found the level shifter at but I need bi-directional level shiter. So I am trying to find out the FPGA board can support 1.8V PMOD. Would you please recommend it? Currently I am seeing Nexys Video has SET_VADJ that can support 1.8V. Can someone please confirm it can support 1.8V PMOD IO? If yes then would you please let me know how to program SET_VADJ to 1.8V?
  25. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <