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Found 211 results

  1. VGA Pmod Tutorials

    Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: Part 2: Bitmap display using your own image: Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will

    I want to interface DAC and ADC with some fpga evaluation board My requirement of ADC and DAC is following DAC input ->sampling_rate=2MS/s frequency=455khz ADC Input ->Signal bandwidth=400khz i have no problem of resolution So someone please guide me or refer me some models of adc and dac along with some FPGA evaluation board that complete my requirements . Also refer me if anyone know about some board that have build in adc dac along with FPGA Any kind of help in this regard would be much appreciable
  3. Hi, I need the .iic file in order to upload the eeprom IC5, where the Cypress CY7C68013A firmware is stored, by means of CyConsole tool. Currently IC5 does not assert the USB-ON signal, which enables the power on the board. Sincerely, Radek (rsip)
  4. FPGA, ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 (24bit@48k), I2S output. DAC will be CS4390 (24bit@48k), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  5. Clarification for FFT implementation in FPGA

    Hi, I am trying to compute FFT of a synthesized square wave of frequency 100Hz. The 100Hz signal has to be sampled at 1kHz. So, I kept the clock frequency of FIFO, FFT_IPcore and other blocks at 1ms. I have attached the screenshot of the design file and simulation results. From the simulation output, it can be observed that the buffer stores for 512 samples and the un-buffer after 512*1ms. But, there is no output from the FFT block. I would like to know whether my approach is correct or I am committing any mistake in the way the blocks have to be integrated. Help much appreciated. Regards, Subash
  6. I want to know how to connect a speaker and it's frequency in fpga to send the data to the speaker...?? Suppose when a lift is go to 1st floor it should make a sound like 1st floor like that . Thanks Vamsi
  7. I am gonna start a project with the following setup (attached the overview). I am doing a scaling function on the FPGA. I was thinking about the Nexys Video Development Board. This board got an DP output. But it only has HDMI as input/output. I know that HDMI is almost DVI. I don't think I can use an adapter. I need the DVI-connector and not HDMI-connection. Prioritized is the DVI--> FPGA--> DP connection. Next comes DP--> FPGA--> DP. I need the DVI input according to the picture. I have been reading about a FMC DVI I/O on Avnet but I can not find it. Any help to solve this hardware/component setup would be much appreciated! (Which FPGAs and FMC to use) Regards
  8. Hi, I want to program my KC705 board with raspberry pi. I have downloaded adpet utilities and adept runtime on raspberry pi. I know python programming but I am not very fluent with c coding. If anyone can help me with programming following modules it will be really helpful to me. programming FPGA with bit files. programming flash with bin file(or any other file format) If possible loading mfs files or elf files on DDR memory.
  9. SPI TFT Display

    Hello everybody. I recently got this SPI TFT display for my Raspberry Pi: But I'd have more use for it in an FPGA project of mine. Now, I couldn't really find a pinout but as it's made for Raspberry Pi I could already figure out what lines are already reserved for power and with a little bit of luck, the MOSI / MISO / SCLK / Chip Select run on these pins: I just wanted to know whether anyone has done this already and / or knows the pinout. Also, what could happen if I put data / voltage on the "wrong" pins? Also, is there something like an IP block that you can use for this type of stuff or would I need to write everything by myself? Thank you in advance! I've never used a display (except VGA) with my board so that's why I ask all these questions....
  10. Labview connectivity to FPGA boards

    What is Digilent providing to support Labview connectivity to your latest FPGA boards? The older Nexys3 board had the Adept software and Labview driver that allowed Labview to communicate to the FPGA board as if it was a simple parallel interface. This is no longer supported by your latest FPGA boards from what I can see. So what do you provide to allow Labview to talk to your FPGA boards?
  11. Hello Digilent, I am just going to buy an ARTY A7 35T board and I have to interface an external ADC ADC7091R with it. I know it has an on board XADC but I need to do for some specific purpose. Now I have seen a Pmod of ADC7091 R given in its datasheet and I want to know that "DO ARTY A7 support pmod of ADC7091R". Thanks
  12. Best software to program an Arty board

    What is the best software to program in C++/C an Arty board? I tried Vivado HLS but it is good only for algorithms not for the components of the board. The SDx made by Xilinx is not compatible with the boards. If are others programs can someone please provide tutorials/books for some examples in C.On Xilinx forum I couldn't find any tutorial for working with the board components in C.
  13. PMODGPIO build on Zybo (2016.4)

    I am attempting to build upon the hdmi demo, here is what I want to accomplish: Take over PMOD_C port as a general purpose digital output (8 pins) Here is what I have done (aside from debugging for hours) I dropped down and wired a PmodGPIO_0 block in my design and connected it to PMOD_C (JC), used the auto-connection automation function in Vivado. The build seems to work just fine, exported hardware, etc as normal. In SDK I get a drivers/ directory in hw_patform_1 with PmodGPIO_v1_0 and everything looks fine. Here are the exact steps I followed from here to where I am now: copied PmodGPIO.h down to hdmi/src (build project directory) copied code (functions) from PmodGPIO.c into video_demo.c (build main .c) copied code (init, main, close) from output_demo.c into appropriate places in video_demo.c Question 1) The code would not execute, because it appears the XPAR_ for PMODGPIO does not feed correctly into xparameters.h. Is this normal? I tried to workaround by checking system.hdf and found the base address for my PMODGPIO 0x40000000 and hard-coded it. This would allow the code to compile, but it does not run correctly, it hangs in GPIO_begin on the statement Xil_Out32(InstancePtr->GPIO_addr+4, bitmap);. This is the first statement where it attempts to write to the mapped memory. I have a feeling that something with the PmodGPIO IP is not building correctly for me, but I don't know how to correct it. I have tried several times to clean and rebuild the project, but again I don't know if I am taking the right steps. Question 2) Is there some type of 'build' that I need to do in SDK or somewhere else to initialize the IP correctly and be able to write to the PmodGPIO ? Thanks!
  14. My first Zybo/7010 project

    Greetings fellow FPGA enthusiasts! I'm looking for eyeballs Specifically digital logic enthusiasts, HDL or otherwise, and maybe even those appreciative of retrocomputing (my first Zybo project is a C64 clone after all). It is my hope I might find some people interested in this project: and perhaps also the associated "Inside the Box" YouTube channel where I am going to attempt to explain aspects of the project to others attempting to learn. I'd like to break that feeling that I'm the only one in the world interested in these things (I know I'm not but experience and YT video visitor stats keep trying to tell me otherwise ).
  15. I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all. I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz. First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?
  16. Hi, I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them??? Thank you...
  17. Hi, I just brought the NEXYS 4 FPGA and want to start learn it myself. The first project I am trying to do is changing the seven segment display one by one. Is there any example code that I can start with? Thank you.
  18. Camera Sensor for Arty Z7-20?

    Hello, I am working on a project using an Z7-20 FPGA for computer vision processing using a CMOS camera sensor. I am planning to run convolutions on the image data for usage such as a Sobel filter. (to avoid RAM requirements, I will most likely use a Line Buffer to store the data while it is in use. This means I will need a camera sensor which can connect directly to the FPGA and outputs one pixel at a time (through multiple wires for each color), with a well-defined (or customizable) clock to synchronize the data transmission. I want like something cheap, rugged, and easy to wire like the OV7670 (as this is for a robot, I cannot use something too sensitive to vibration), but something that has a little higher resolution and framerate (I was thinking 480p or 720p at 60fps, or 1080p at 30fps, but lower is fine if the price is too expensive), as well as being a breakout board which can be easily wired (I can make a custom pin header adapter from the camera module to the FPGA's ports if needed, but I don't want to have to use a very small/thin one or something that requires SMD soldering). Any suggestions? Thanks in advance.
  19. Filter using FIR compiler RFD is delayed

    I have build filter using FIR compiler. It is filtering the input quite well. I used COE generated from Matlab. I have two problems. 1- filter latency is 39 cycles. I am getting my RDY signal high after around 39 cycles. But RFD gets high after 251 cycles? I don't understand , if filter is giving me RDY signal high then according to FIR compiler datasheet figure of MAC multiplier timings, i should get RFD as soon as RDY gets high. I have tried both systolic and transpose MAC. I am attaching the figures from chip-scope. ZOOM-IN of ND-RFD ZOOM-IN of RDY ZOOM-OUT including two RFDs I want to get RFD as soon as my filter output is ready. Any clue ! 2.All is fine. filtering is good. I am using filter range from 900hz-3300hz. I am getting TICK like sound after some 500msec. I saw it on oscilloscope it is some type of clipped signal containing 5-6 cycles of not any specific frequency. the signal is looking more like square wave due to clipping. I am getting that TICK sound even if I did not attach LINE IN cable (from which data is fed to filter input through CODEC). But if I programmed the input of filter to '0' in verilog, I get nothing. Tick sound is also removed now . Filter is generating tick sound in any other condition, What is this? am I getting overflow some where? Thanks
  20. Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is an inout port. First, a little background: The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call it o_clk. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. The o_clk is looped back from the FPGA's output and is given to another ball as an input clock, let's call it i_clk. The external chip receives the o_clk and sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped back i_clk. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is an inout port). Something like below: FPGA --> EC is synchronous to FPGA because FPGA generates clock EC --> FPGA is synchronous to EC because FPGA gets external clock (virtually from EC) To constrain this design, I have used the i_clk to set input delays on the io_data and have used the o_clk to constrain output on the same io_data bus. I have made sure I am using a forwarded clock (create_generated_clock)(using the ODDR2) for the set_output_delay constraint. Here are my constraints: create_clock -period 10.000 -name i_clk -waveform {0.000 5.000} [get_ports i_clk] set_clock_groups -name loopback_grp -asynchronous -group [get_clocks i_clk] -group [get_clocks o_clk] set_input_delay -clock i_fx3_pclk -max 8.000 [get_ports io_fx3_fdata] set_input_delay -clock i_clk -min 2.000 [get_ports io_data] set_output_delay -clock o_clk -max 2.000 [get_ports io_data] set_output_delay -clock o_clk -min -0.500 [get_ports io_data] The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design. My questions are: Have I designed a good system? Is it correct to treat the communication from EC --> FPGA as source synchronous? (The other direction is source sync because FPGA is providing clock, if I am not wrong.!) Are my constrains correct? Many thanks!
  21. Matrix reception module in vhdl

    Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab). Thank you for your attention
  22. I am trying to load my program to a Block RAM using Data2mem, after the bitfile is generated. Here are the steps: I have generated a BLOCK RAM as single port ROM with 32 bit-width and 16384 bit-depth. Then translated the design without any BMM file and looked at the PlanAhead tool to see which BRAM are used and which ramloop is assigned. There are 15 ramloop lines. There are 14 PRIM36 primitives and 1 PRIM18 primitive as shown below: BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP **(RAMB18)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP **(RAMB36_EXP)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) I wrote the following .BMM file for address the ROM from 0x0000 to 0xFFFF. and add it to the xilinx project. ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff] BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; END_ADDRESS_SPACE; But when I tried to compile it again it gives me the error: ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE 'pr_mem1'. Can you please help me out where the error is occurring? Is ramloop[xx] correctly used?
  23. Non-clocked synchronous circuits

    I was reading Dan Gisselquest's blog (aka @D@n), in particular, this specific part of the one that goes into some detail about the ALU for his ZipCPU: always @(posedge i_clk) if (i_ce) begin c <= 1'b0; casez(i_op) 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB 4'b0001: o_c <= i_a & i_b; // BTST/And 4'b0010:{c,o_c } <= i_a + i_b; // Add 4'b0011: o_c <= i_a | i_b; // Or 4'b0100: o_c <= i_a ^ i_b; // Xor 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR 4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL 4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR 4'b1000: o_c <= w_brev_result; // BREV 4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO 4'b1010: o_c <= mpy_result[63:32]; // MPYHU 4'b1011: o_c <= mpy_result[63:32]; // MPYHS 4'b1100: o_c <= mpy_result[31:0]; // MPY default: o_c <= i_b; // MOV, LDI endcase end else // if (mpydone) // set the carry based upon a multiply result o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; Dan makes the comment: "Each of the blocks in this figure takes up logic when implemented within hardware. As a result, even if i_op requests that the two values be subtracted, all of the other operations (addition, and, or, xor, etc.) will still be calculated. These other results, though, are just ignored. Thus, on the final clock of the ALU, all of the operations have been calculated, but only the result of the selected operation is stored into the output register." (bold emphasis mine) I found this a very interesting comment. Dan shows how there is effectively a multiplexer based on the opcode on the output of each of the logic chains. It strikes me that this is quite a waste of power, in general, so I wondered how, or even if it is possible to do things differently. Using one of the ZipCPU ops as an example, could one reliably implement something like the following? always @(posedge i_clk) if (i_ce) begin do_cmp_sub_op <= (i_op == 4'b0000) ? 1'b1 : 1'b0; ... rest of the op codes go here ... always @(posedge do_cmp_sub_op) begin {c,o_c } <= {1'b0,i_a}-{1'b0,i_b}; do_cmp_sub_op <= 1'b0; end There are many reasons why this is not something you would do in real life in a CPU, among other downsides it would have the effect of adding extra logic and an additional (at least) 2-clock latency right as the rising edge of the various do_xxxx registers would be one cycle behind, plus you'd need another cycle to turn the clock off so that you could catch a rising edge. So clearly this isn't something one would do for CPU ops that only take 1 cycle. 1) What are the various ways to only have some of the gates / logic working in a system while most of it is quiescent and only run when needed? 2) Does an if statement have the same logic as the case in this respect, i.e. does the logic for i_ce is 1, and i_ce is 0, also both get run but discarded on the input side of a multiplexer as well? 3) What are the options and tradeoffs involved in deciding what to use as the triggers for logic?
  24. AXI DMA

    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. Any help is appreciates Best regards,
  25. Hi all, May I humbly ask the experts in this forum if you already tried to implement AT commands into FPGA to make the cellular module works and be able to use the internet inside the FPGA. Ours, want to implement the cellular module via RS 232 interface into the pmod zedboard. Hoping for some guidance on how to go through it. Thank you in advance. Best regards, Glenn