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Found 179 results

  1. Zybo: Access the LD_MIO LED from the FPGA

    Hi, I have a Zybo board and am using Vivado 2017.2. I have successfully written a number of VHDL modules allowing me to access the boards push-buttons, LEDs and slide switches using only the PL part of the device. I wondered if it was all possible to drive the LD_MIO LED from the FPGA? From my understanding it should be possible using the EMIO but have not been able to find an example or tutorial that shows how it is done. Regards FarmerJo
  2. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  3. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  4. motor controller with BASYS3 and UART

    Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  5. Cmod A7 Clocking

    The schematic diagram for the Cmod A7 shows a clock with part number ASEM1-100.000MHZ-LC-T, which is a 100MHz clock. However when I look at the actual clock component it says it's 12MHz chip, which I confirmed by scoping the output. Is there any way to get a 100MHz clock signal out of this board?
  6. Dividing by 10....

    Tonight I discovered that this is a fast way to divide by 10 unsigned div10(unsigned x) { #ifdef REF /* Implement 32-bit division using divide */ return x/10; #else return (x * 0xCCCCCCCDLLU)>>35; #endif } Just wanted to post it here in case it becomes of use to somebody. A variant It could most likely be used with a DSP48 block to divide shorter (20 or 23 bit) binary numbers with much less resources and latency than a 10-bit binary divider.
  7. arty Z& petalinux BSP Error

    Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  8. Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  9. SPI Interface -> Quad-SPI Flash.

    hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  10. UART communication protocol in nexys 4 DDR for XADC

    Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  11. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  12. I am currently using nexys 4, I want to input console inputs to my VHDL design. I know that ISE uses a .ucf file where the inputs and outputs of the card are assigned, however my interest is not to use the inputs provided by the card and I do not know how to assign these inputs sent from an application, I would thank anyone who can help.
  13. FPGA design contractor

    Hello, We are a company based in Pittsburgh, Pennsylvania, and we are looking for a contractor who has experience with FPGA design work. Thank you.
  14. Hi all, We are looking to use the Arty board for first tests on a machine vision system we are developing, which runs a 72 MHz parallel interface. For ease of testing I was planning to use the Arty board and its I/Os, but I see that it has 200 Ohm series resistors on each pin which will put a limit on the max allowed switching speed. Are there any specifications on the pins when it comes to speed? With 200 Ohms about 5-8 pF is maximum allowed after the resistor for a 72 MHz signal. Else, as I do not have the board yet, are the resistors easy to get to (silkscreen designators for correct identification) to replace the resistors manually with a lower value? Thank you for your time!
  15. create sine wave on dac using vhdl

    i want to generate sine wave on dac (pmodda3)( i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  16. SGTL5000 + PMOD CMOD-A7

    Hi! I've hooked up a CMOD-A7 to an audio codec board designed for the Raspberry Pi, getting ready to play with some audio. You can find the VHDL source at It is still rough and ready, but it works
  17. LPC-FMC to FMC connection between ADC & ZEDBOARD

    hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  18. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  19. Centos Vivado Xilinx JTAG Cable

    Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  20. 1.What is the exact difference between the board and the platform? 2.Are there usable platforms without SoC or any processor on them? 3. How can be the boards connected to each other?
  21. Where can I see the relations between the Arty Z7 board pins (I/O) and the FPGA pins? In "Arty Z7 Reference Manual" it is not enough information: only buttons, slide switches, LEDs and HDMI pins relations appear. (eg. BTN0 is D19) What about the rest of the pins (I/O)?
  22. Hai ., i had bought DIGILENT Zybo Kit 7000 series Family. i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4) fsbl.elf system_wrapper.bit U-boot.elf U-image 0x600000 dtb file 0xA00000 ramdisk 0xA20000 But the FPGA done_led is not working automatically after a power cycle. on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads successfully from QSPI Flash. How to Make FPGA done_LED works automatically? Thanks in Advance..
  23. First Arty7 Project Program FPGA Failed

    Hi All, I have been working through the Arty - Getting Started with Microblaze project in the resource folder with the Artix-7 FPGA Development Board. When I get to step 11.2 Program the FPGA I get the following message Program FPGA failed Reason: Could not find FPGA device on the board for connection 'Local'. I have been stuck here for the last couple week and have tried several times to track down the connection issue. So far no luck. Any assistance would be greatly appreciated. Thanks, Don
  24. Hello everybody! I just finished a series of posts on describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA. Examples include how you can read or write FPGA block RAM, or even an internal scope. Today's post described how to build a software facility for accessing memory mapped I/O components within your design. Hence, you can issue read and write commands from your host PC software to access the internals of your design. In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example). It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs. Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more. In addition to the articles on, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design. Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs. Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design. Dan
  25. Timer on bare metal app

    Hi, I want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC(zedboard). I included "xtime_l.h" and used XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) to populate tStart and tEnd. The difference tEnd – tStart always gives me 0 for whatever instructions I put between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd). Instructions between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) that I put are: ————————————- XTime_GetTime(&tStart); print(“Hello World\n\r”); for(int i=0;i< 1000 ;i++) { sum += i; } Xil_Out32(0x43c00000, 0x5); Xil_Out32(0x7aa00000, 0x5555); NumberOfPattern = Xil_In32(0x43c00004); XTime_GetTime(&tEnd) ————————————- I need to mention that i did not configure the PL part to include an axi_timer IP. I did not do this because, as i read, this uses the global timer in the zynq Soc whose counter increases every two clock cycles. Can someone to show me where is the mistake and give me some advices?