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  1. Hi, I want to create a test pattern generator project that uses the TPG IP to display the test patterns on the monitor via HDMI. For this I have been referring the Xilinx Video Series 19, however, the hardware used in the video is ZC702 and the hardware I am using is Zybo Z7-10. I also checked the HDMI demo available for Zybo Z7-10 but it does not include the TPG IP. Kindly suggest how can I achieve the same. I tried to replicate the block design from the video series 19 and made a few changes but I am not sure about it and got a few errors. I have attached the block diagram image an
  2. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20
  3. Hi all, Maybe it's just a small detail that is missing but I don't know how to solve it exactly. I’m trying to communicate my laptop with my ZedBoard but for some reason, it suddenly stops. I follow the procedure indicated in instructions included with the ZedBoard package and are also indicated in this tutorial. I download the USB to UART adapter driver (controller version 3.13.0.59) by Cypress which controls the USB serial port (in this case COM9). The device is identified as Cypress-USB2UART-Ver1.0G. The settings form COM9 are like the figures. When I turn on the ZedBoard wi
  4. Hi, I have Basys 3 for SPI slave and it supports 3.3 PMOD IO but I have 1.8V SPI Master So I need to have a way to use 1.8V PMOD. I went through the forum and found the level shifter at https://store.digilentinc.com/pmod-lvlshft-logic-level-shifter/ but I need bi-directional level shiter. So I am trying to find out the FPGA board can support 1.8V PMOD. Would you please recommend it? Currently I am seeing Nexys Video has SET_VADJ that can support 1.8V. Can someone please confirm it can support 1.8V PMOD IO? If yes then would you please let me know how to program SET_VADJ to 1.8V?
  5. hello, i am implementing image processing on Xilinx Basys 3 board for which i am using microblaze. I have created an image processing ip which will be reading and writing data through a DMA to microblaze. But i not not sure which is the right way to connect my DMA to microblaze. If i am using Zynq PS i would be using HP mode or slave ACP pin to connect with my DMA but have no idea how to do the same in MicroBlaze.
  6. in my design i need to calculate an array containing a waveform, (a sine for this example) inputs of the block would be a memory containing an index of 1024 samples and a user-related period value. output would be an array of 1024 samples written on ram being amplitude and phase fixed the expression to calculate the single sample of the waveform would be x = sin ( period * index (0-1023)) Could I instantiate 1024 blocks so that the samples of the resulting array could be calculated concurrently?
  7. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  8. Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY. My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE pa
  9. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some
  10. Pier

    Zybo z7 evaluation

    How could be possible to implement the design shown in attached video? in the video the arrays are 600 samples each, but i would go for bigger arrays as possible and 24 or 32 bit values i'm planning to use a zybo z7 board exxample.mp4
  11. Hi. I've tried to operate Pcam-5c at Zybo-Z7-zynq7020 using Xilinx Vivado tool. I refered to source code for Pcam-5c posted on github( https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases ). It operated successfully but I want to try again using other camera module instead of Pcam-5c. I have some problems in MIPI formatting data because Zybo7020 & Pcam-5c use RAW10 data but my camera module use RAW12 data. How can I use RAW12 format with Zybo-Z7-20 ?
  12. I think my question is general but i want to know how to initialize Pmod OledRGB using case when-statment i found some vhdl codes using this method but i cant understand it
  13. I am looking to start developing a new setup and I purchased the USB104 A7 and Zmod ADC1410 as shown in the picture and can not find a simple way to get this up and running to see if it meets my criteria. The ones that are linked there are for a different development system and require an Ethernet port. Can you guide me to the proper resources? Best, R
  14. Hi, I have lost firmware for Nexys 2 USB Controller (CY7C68013A-56) which is stored on 24AA128-EEPROM. I want to update it by CyConsole application. Could anybody help? Thanks
  15. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  16. Due to the nature of my project, I need to program the cmod a6 with the use of a JTAG programmer. I have a HS2, which is configured AND recognized by iMPACT AND Adept. Unfortunately, when I attempt to program the cmod a6 board, I get the following: // *** BATCH CMD : Program -p 1 -dataWidth 4 -spionly -e -v -loadfpga INFO:iMPACT:583 - '0': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '0': Device IDCODE : 00001111111111111111111111111111 INFO:iMPACT:1579 - '0': Expected IDCODE: 00000100000000000000000010010011 PROGRESS_S
  17. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about
  18. Dear friends, We have intended to use the JTAG-SMT3-NC module for both FPGA and ARM MCU programming. Our planned configuration is channel A for FPGA programming and channel B for ARM MCU programming. Do you please notify us if we are capable to perform the above work or not? Also, can we configure as JTAG the both channels (A and B)of the JTAG-SMT3-NC module with FT_PROG software. If not, please advise the solution. Also you can submit your tender to eliminate this difficulty. Attached please find the our working configuration. Wait for your response.
  19. Hi, I'm a newbie trying to learn about the Genesys 2 board and would like to program the onboard OLED as an exercise. I'm following this tutorial. There is a prominent warning that says "Important! Make sure to turn off the OLED display before shutting down or reprogramming your board." Why? What will happen if I don't turn off the OLED display and simply turn off the power switch? Will it get damaged? This makes me very nervous to try my own programs since I will probably mess up at some point. Can someone reassure me that I won't do any permanent damage? Thanks!
  20. Hello, I have a NetFPGA 1G-CML board and in my new project I will have to use Vitis Accelered Libraries. So, I would like to know if I can use Vitis Accelerated Libraries on a NetFPGA 1G-CML board. If I can't use it on NetFPGA 1G-CML, what would be the best board option? Thank you
  21. Hello, (FPGA board is Nexys A7 100T) So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results. Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
  22. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code,
  23. I tried to do this Pong game project https://github.com/CynicalApe/BASYS3-PONG and connect VGA to monitor. But monitor keeps flashing. Video im not sure if this problem appear because i have connected Basys3-> VGA adapter to hdmi -> wire hdmi to mini hdmi. Because my screen has only mini hdmi port.
  24. Hi, I've got my Arty sending out UDP packets to my laptop, without any soft CPU involvement. I've still got to add checksums and so on, but at least it works! http://hamsterworks.co.nz/mediawiki/index.php/ArtyEthernet
  25. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.