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Found 238 results

  1. HDMI_IN Arty Z7-20 ERROR

    Bonjour, J'ai testé le code du projet HDMI_IN publié sur le GitHub d'ici sur la version 2016.4 de Vivado et j'ai eu cette erreur ! any Help !
  2. Basys3 Boards Problem

    Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator. Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it. Thanks
  3. Bonjour, je travail cette période sur le hdmi_out de la carte fpga arty z7-20, et comme tout le monde j'ai commencé par télécharger le fichier tuto de .git, deja apres l'implémentation y a rien qui s'affiche sur le deuxieme écran donc j'ai essayé de modifier les blocs IP par l'ajout d'un bloc qui convertit une image à une matrice et le lié avec le reste des blocs en appliquant les modifications nécessaires sur le BD et le .vhd , finalement, j'ai obtenue cette erreur. Remarque à savoir : j'ai vérifié les liaisons en RTL design et elles me paraits correctes MErci pour vos aides, translated by google translate by JPEYRON Hello, I work this period on the hdmi_out of the art7 zp-20 fpga card, and like everyone else I started by downloading the .git tutorial file, already after the implementation there is nothing that appears on the second screen so I tried to modify the IP blocks by adding a block that converts an image to a matrix and binds it with the rest of the blocks by applying the necessary modifications on the BD and the .vhd, finally, I got this error. Note: I checked the links in RTL design and they seem correct to me MErci for your help,
  4. Hello guys, I need two clock outputs operating at 6 GHz with an adjustable phase difference. Is it possible to obtain such outputs with Genesys 2 kintex-7 FPGA? I could not find anything related to this in the manual. Regards, pnsak.
  5. I tried to synthesise the Zybo HDMI In project https://github.com/Digilent/Zybo-hdmi-in for the latest Vivado 2017.4.1. Without changing anything from the Block design and just upgrading all IP Cores in order to start the synthesis, the timing will not be met: Slack: - 6.327 ns The IP Cores are generated globally. How I can fix this problem?
  6. Reference design for mouse overlay

    hello, I am interested in the following reference design: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-vga-test-pattern-with-mouse-overlay/start The design currently does not provide any sources: Is this project abandoned? I believe it had not been updated since 2015. Is there a later version available (this one, perhaps, or on github?) I am interested in the USB host with mouse, which I intend to implement on the Zybo/Zybo-Z7. Do you provide the sources for this project? Is there a project you can recommend, There is also the BIST for the Zybo-Z7, maybe it contains relevant references? thank you
  7. PmodWifi fails to connect and overheats

    I run the httpserver on an Arty board and I get in console WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Timeout occured Shutting down Resting for 30 seconds 30 seconds until restart 10 seconds until restart Done resting WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Timeout occured Shutting down Resting for 30 seconds 30 seconds until restart 10 seconds until restart Done resting WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Not Initialized Hard Error status 0x10011007 occurred. Shutting down Resting for 30 seconds 30 seconds until restart 20 seconds until restart So I don't get anymore Network initialized .What can cause this problem?The Pmod also overheats.
  8. no console in ttyPS0 : zybo 7010

    Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  9. FPGA with really much RAM

    Hi everyone, this is my very first question on your forum I'm new to the FPGA topic and this week I struggled to evaluate how difficult the following project will be: We have a motion capture system tracking a hand and driving a very complicated levitation device. The project should work with as little delay as possible. At the moment it is about 17 ms and the target is to reduce this to around 7 ms. Most of the latency comes from the GigE connected cameras, sampling at 200 Hz, but also from the operating system. Because of the complex computation, the difficult part is precomputed as a very big lookup table (8 GB) present in memory. To reduce latency, we want to work 'bare metal' and later on , eliminate the lookup table and use high parallelized code to drive 128 devices at 50kHz frequency. What I planned so far: Using the existing cameras would require a low latency system handling image processing (stereo camera registration and key point tracking). I know that these would be efficient to be implemented on an FPGA. To address 4 Optitrack Prime 13 cameras, the NetFPGA-1G-CML Kintex-7 FPGA Development Board looks very promising. Can somebody estimate how difficult it will be to extract images of a GigE Camera with the Vivado Studio will be? The second part is frustating: I do not know how to add DDR3 RAM from a laptop to this setup. Is it possible to add an adapter to the FMC and use the MIG to configure the Interface? I tried to search for this but only found boards with SO-DIMM sockets or RAM -Chips presolderd. The first are far to expensive and the second have not the required capacity. I only used SPI and I2C on a microcontroller so far, therefore interfacing ethernet phy or RAM programmatically and especially physically is still a mystery to me. The third problem is optional: the target device is interfaced via USB 2 and drivers only exist for Windows. It is not easily possible to communicate directly with an FPGA in this scenario is it? In the end, I want to use high level programming, like the Vivado Studio or Simulink. The project is financially limited, but around 2000 Euro would be adequate, my professor told me. I am thankful for all constructive advices, comments. literature and questions. Please tell me your opinion, if an FPGA will be the right choice, the project is manageable and/or if there is a better solution. Best regards from Germany, Matthias Popp
  10. Delay

    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  11. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: http://www.elpcctv.com/mi5100-5mp-usb-camera-module-usb20-aptina-125inch-color-cmos-sensor-100degree-lens-p-221.html CSI-2 Camera: https://www.waveshare.com/product/rpi-camera-f.htm DLP 2000 RGB - projector: http://www.ti.com/tool/DLPDLCR2000EVM HDMI projector: https://www.ebay.in/itm/302673956725?aff_source=Sok-Goog Display : https://www.alibaba.com/product-detail/5-inch-720p-oled-display-720_1925219941.html?spm=a2700.7724838.2017115.42.6ba11d77AqfGq7 Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  12. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  13. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  14. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  15. Bonjour à tous, je travaille sur un projet dans le but de detecter la position du moteur à travers d'un flux d'image ou video de l'entree HDMI de la carte FPGA. cette position genere le singnal d'entrée des LEDs pour les allumer. du coup je travaille maintenant sur la conversion de la matrice en coordonnées polaire en coordonnées cartesiennes. y a t'il des documents ou des idées pour programmer le code ?? merci en avance. Translated to English: Hello everyone, I am working on a project in order to detect the position of the engine through an image or video stream of the HDMI input of the FPGA card. this position generates the input singnal of the LEDs to light them. So I am now working on the conversion of the matrix into polar coordinates into Cartesian coordinates. are there any documents or ideas for programming the code ?? thank you in advance.
  16. Linux image for Zybo Z-10

    Hi all, I m a beginner in FPGA. Last month I got a Zybo Z-10 board from diligent web store. Started working on it using Vivado 2017 edition. I played with leds and switches in PL section. Now I want to run linux image on this board. I tried many tuturials which showing how to boot zybo with linux. but failed. As in the tutorials, I created sdcard with two partitions, one with ext4 and another with fat and then I copied devicetree files, boot files etc in one partition and linux files in another partition. When I boot the board with sdcard monitor shows a black screen with some text like petalinux 2015, zybo login etc. Actually i dont know how the it boot up with linux in zybo board. I dont know whether this screen which I got is correct screen or not. Can anyone help me to boot a linux from my zybo z-10 board Thanks in advance.
  17. Parallel FPGA JTAG programming

    The attached image is probably the easiest way to ask this question .. We want to program 6 devices all at the same time using 6 copies of a USB-JTAG device (as opposed to having once large JTAG chain). It looks like Impact / Vivado does not natively support this (it sees multiple dongles but only deal with them one at a time). Can we script something to load a BIT file on all 6 simultaneously? We currently have the XUP USB-JTAG Programming Cable but would switch to another one if this one can't do it. Thanks!
  18. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  19. hi.. ! I need a fpga devolpment board with VGA and HDMI as input and HDMI or DVI or both as output. i googled but not find a single board with these connectors together. Thanks in Advance.
  20. FPGA SPI transfer timed out

    Hi all, I'm having an issue with the FPGA SPI interface I programmed onto my microzed. The issue is that the interface cannot read the data sent back from my slave device! I'm using a SAMA5d3-xplained devboard, and an oscilloscope to measure signals. I made the SAMA return the same buffer it received, only with every byte shifted. So it's a semi-loopback routine. The oscilloscope captures both the correct signal back from the SAMA (every byte divided by 2), AND the signal going into it (out of the MicroZed). However, the spidev_test.c (that seemingly famous SPI testing utility on the torvalds repository (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) program that I'm using shows one of two things: 1. Either the result is always an error of "SPI transfer timed out" 2. or the value in rx is the same as in tx. That is, even though the SAMA slave is demonstrably (via oscilloscope) returning something else, all the RX buffer gets is the same as was sent via the TX buffer. In fact, I can even disconnect the header that plugs the master to the slave, and this behavior becomes no different. The difference between these two results is simply a matter of removing the 1050th line in drivers/spi/spi.c when building the kernel. It's the call to wait_for_completion_timeout() in the function static int spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *msg). What I get from this is basically that the spi-xilinx.c driver does not know where to look for the output from the slave (MISO), and it either waits eternally for that output (if the call to wait_for_completion is left intact) OR it doesn't care to look for the data and just fills the rx buffer with the tx buffer. Now I have a very limited understanding of hardware and driver programming, so I'm basically like a blind man in the dark here. I'm adding printk() statements to spi-xilinx.c and spi.c everywhere, and checking their results with dmesg and there's just nothing enlightening (I'm using PetaLinux, and the devices all show up correctly in /dev and /sys). I'm hoping someone more experienced can shine a light on what I'm doing wrong here, or at least point me in the right direction. Attached is my device tree file, plus a screenshot of the hardware design. (the relevant node in the DT is highlighted below) amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "simple-bus"; ranges; axi_quad_spi@41e00000 { bits-per-word = <0x8>; compatible = "xlnx,xps-spi-2.00.a"; clock-names = "axi_clk", "spi_clk"; clocks = <0x1 0xf>, <0x1 0xf>; fifo-size = <0x10>; interrupt-parent = <0x4>; interrupts = <0x0 0x1d 0x1>; num-cs = <0x1>; reg = <0x41e00000 0x10000>; xlnx,num-ss-bits = <0x1>; xlnx,spi-mode = <0x0>; spidev@0 { compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x17d7840>; }; }; }; goodVersion1.dts
  21. Hi, I have lost firmware for Nexys 2 USB Controller (CY7C68013A-56) which is stored on 24AA128-EEPROM. I want to update it by CyConsole application. Could anybody help? Thanks
  22. C Code to read/write to DDR

    Hello, so I followed this axi-dma tutorial and everything looks pretty fine. Now, this tutorial only goes to running a HelloWorld application inside de XSDK. I would like to know how t write something to DDR and how to read something back (specifying addresses e.g.)? To be precise this is how the actual design looks like I would really appreciate some sample C code of how to instantiate (?) the AXI Slave/Master ports to be able to read something from the DDR. Thanks !!
  23. Help needed with FPGA programming

    Hello guys, Some time ago I've watched a talk of the nand2tetris course/project. If you've never heard of it you can check it out here: http://www.nand2tetris.org/. Basically it is a course designed to build a computer from the very ground up. It starts with logic gates and goes all the way up to programming a small game project (hence the name nand2tetris). I've always been curious about doing something with FPGA hardware, but never had any idea of a feasible, yet interesting-result-yielding project. Well, as you can probably guess, up until now that is. During my university days I attended an FPGA workshop and I've read some stuff about the hardware components and the available course material such as Basic Introduction and Design flow of Programmable Logic Device FPGA. If you need to pick up something relating to the PLD or FPGA, you can check it out here: http://www.apogeeweb.net/article/67.html. So I think I kind of have an idea about the difficulty of the project. But since everything I've been reading just made me more excited, I decided I absolutely want to give this a shot. Now there's a lot of FPGA information out there, so I'm surely still missing a lot of important information, but I would like to get started and think the best way to learn is to actually experiment with a real FPGA instead of wasting too much time with HDL simulations only to become used to functions that aren't going to synthesize on the board anyway. So I now would like to ask you about some things I'm still unsure about and would like to have clarified before buying an expensive development kit. I've read several articles about Altera and Xilinx and right now my choice would be a Spartan 3E Starter Board - this one to be exact: https://store.digilentinc.com/spartan-3e-starter-board-limited-time/ The main questions I'm having right now: Is there a general reason that would argue against getting the Spartan E3 board? I actually have no idea how powerful an FPGA really is, but assuming it's running on Cyclone II hardware, it probably should run on a Spartan 3 as well? Or is that in itself already a stupid question, as FPGA comparison doesn't work so easily? In general, who is more newbie-friendly, Altera or Xilinx? (I've worked with VHDL before, which I think is Xilinx, right? Altera's Quartus is probably very similar?) From how I understand the FPGA toolchain, in the above linked offer there should be everything included to get me going. right? I also have this second candidate: http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS Maybe I'm an idiot, but as I read the offer, *only* the board is sold? I.e., in contrast to the first offer, I would need additional stuff to get something running on the board? It also strikes me as a mayor drawback that there is not really an output option besides a few LEDs. which for me would be very annoying; I'm already unhappy about the board linked before *only* having a small display (which in itself, however, is awesome to have of course). This might also be a stupid question: I remember from back in the FPGA workshop I mentioned that getting a number-display to run is not that hard at all. How much more effort is it to get something displayed on a screen (either an attached one or a PC screen accessed via one of the available ports)? And as a final question: I've also seen some very much smaller boards than the ones linked here, that are also much cheaper. Are the boards I'm looking it overkill for what I'd like to do with them? Or does actually the contrary hold, and such a project wouldn't even run on one of the smaller boards available? Regards, Joshua
  24. Convert FPGA active low logic to active high

    Hello, I am using xilinx spartan 6 sp6-x9 board in which its led's and switch works on active low logic. Is it possible to convert switch and leds to to active high logic