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Found 269 results

  1. Flux

    VGA Pmod Tutorials

    Hello, I've been having a lot of fun with the VGA Pmod. I thought other forum members might appreciate a couple of tutorials I've produced with it. Part 1: Intro to VGA and basic animation: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 Part 2: Bitmap display using your own image: https://timetoexplore.net/blog/arty-fpga-vga-verilog-02 Both are written in pure Verilog, so it's (hopefully) easy to understand what's going on and adapt for your own projects. Feedback welcome, Will
  2. John1123

    ARTY FPGA

    Hi, I don't really know where to post this but I have a question. I am very new to FPGAs so this may seem as a very stupid question. i wanted to use my ARTY and read values from the analog IO and output the values through UART. I am familiar with setting up UART and microblaze but I have no idea how to use the analog IO. Any help will be kindly appreciated.
  3. I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip
  4. I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
  5. Which are the choices to learn about network message processing in FPGA? I would like to get a couple of FPGA cards, to allow students to learn about low latency network message processing. My assumption is that the Ethernet port must be connected directly to the FPGA. Is this correct? If that is correct, then it seems that low cost solutions like the Arm based Zinq are not appropriate, as the network port is connected to the ARM CPU, and not directly to the FPGA. So far, the only card I could find where this 'direct connect' is stated, is the NetFPGA 1G card, at around 1,500 usd, Are there any lower cost options?
  6. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx
  7. Hello all, some months ago I had a Basys 2 Board that I perfectly could program via multisim, designing an schematic and then exporting the design. Now I have an Arty S7 on my hands and I would wish to do the same. I followed the tutorials: http://www.ni.com/tutorial/14871/en/ and https://reference.digilentinc.com/learn/programmable-logic/tutorials/program_fpgas_through_multisim/start An instance for the Arty S7 was created in multisim and it gave me the option to generate the VHDL file from the design (I haven't verified the file yet). Multisim won't give me the programming option. I checked the configuration files for others working boards and there is a missing line for programming, like Device ID etc. Mi question, does anybody has tested programming the arty s7 from multisim? if not is it possible? directions ? Best Regards, Edwin Marte
  8. tiago0297

    Axi DMA always busy

    Hi, I'm doing a project that uses AXI DMA. I already done my Ip Core, my Block Design e and my SDK code. The problem is that when my program reaches while(XAxiDma_Busy(&axiDma, XAXIDMA_DMA_TO_DEVICE)) it gets stuck. I'm using a Zedboard and Vivado 2017.4. I did a search, found out that it's a very popular problem, but I had no success solving it, so I'm posting here trying to get more help. I'm attaching my sources. Thank you srcs.zip
  9. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks
  10. Hello, I am searching for new FPGA development board to replace old Virtex-5 OpenSPARC XUPV5 board (ML509) which retired. https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentXUPV5Board.html https://store.digilentinc.com/virtex-5-opensparc-fpga-development-board-ml509-retired/ What is the most similar board which is being sold now? Thank you.
  11. Hello, I am working on a dual core project with mailbox IP on a Arty Z7-10 board which has been acting inconsistently. In my project, 1st core is receiving data from FPGA and sending it through mailbox to the 2nd core; the 2nd core is supposed to receive and write them to the SD card. I need to write the data at 0.5 to 1 MB/s speed, so I can not read and write fast enough on one core. As an example to show the problem, I am writing a number to the card that is being incremented by one on a loop, and plot that versus the clock cycles. Supposedly, my output should look like a straight line which it does if I do all of this on one core. Now, If I use the mailbox to send the same value between two cores, and write it on the 2nd core, I am seeing gaps and overlaps in my data which I am pretty sure is because of Mailbox. Here are two examples of what is happening. If you zoom into the time = 1.0, you can see the following gaps, and overlaps. I have set the size of mailbox at 2048, and made sure that it never fills up by checking its status on every loop. So I wonder what could be the reason for these gaps and overlaps? Can't Mailbox IP transfer data consistently between two cores? Is there any other method for doing such jobs? Thanks, Mahdi
  12. Hello! I'm using an Arty-S7 with a PMODOLED. I want to draw several rectangles on the little display, but the example design seems to delete the previous rectangle when I add a new one. Is there some magic to display multiple rectangles or do I need to dig deeper and hack on OledGrph.c? Thanks! Craig
  13. CraigA

    Multiple PMODOLED

    Hi There, I'm using an Arty-S7 board and am connecting PMODOLEDs to all 4 PMOD connecters (JA, JB, JC, JD). The example that comes with the driver only talks to the PMOD connected to JA, and it works like a champ. Looking at the code and header files, though, I'm not seeing how to talk to the other PMODs. What should I change to talk to the PMODOLEDs on JB, JC or JD. Be gentle, I'm really a hardware guy and using this to learn a little more about C-programming and to that end, the less amount of hacking needed the better. Thanks! Craig
  14. emarte

    Problem wih Arty S7-50 mapping I/o Pins

    Hello All! I have a Arty S7-50 Rev B Board. I am trying to control a mobile robot . I am also using a camera and to talk to both of them I need either I2c or serial communication. So far I created my system using microblaze with no problem. I tested leds, buttons, uart communication etc. My problem comes when I try to map pins other than buttons, leds or switch. I haven't been able to put the system to work. I Tried testing all I could think of before coming to the forums. I saved the project as another one, Created a new one from scratch etc etc and nothing so far. It have been many days if not weeks working in this part. I am pretty confidence about my design and about what I have to do with the robot. What I can't not is get signals out. So at this moment I'll give you some print screen of what I have. I could have some mistakes but it have been a lot of copy and paste and change so I got nowhere to go. I hope some of you could point me on where or how to go. I have this system with all this IP but at the beginning I was testing one by one. I need wither 2 uartlite o 1 I2c working. I know the microblaze, gpio0, timer and interrupt is working. Constraints: I had played a lot with this, this is the las I got. ## Switches set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0] set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1] set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2] set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3] ## Buttons set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0] set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1] set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2] set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3] ## Pmod Header JA #//set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { led2 }]; #IO_L4P_T0_D04_14 Sch=ja_p[1] ## Pmod Header JD ##//set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jap }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33] set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { tx_1 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32] set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { rx_1 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31] set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { tx_0 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27] set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { rx_0 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26] set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { leds[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { leds[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { leds[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { leds[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## USB-UART Interface set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in ## ChipKit I2C set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34] Schematic Elaborated Design: From what I see eveything it is fine, isn't it ? I/O Pots on Schematic I/O Ports on Synthesized Design Code of Sliding LEDS using timer on LEDS: This is funny, these are some sliding leds. It does not matter where I put / map this pins on contraints, this always light the leds. I was tring to map this in pmod header JD but it just ligh the leds. Serial Test: Here the USB serial workf fine with the PC but the other 2 are sending nothing. I2C selftest. The selftest failed, I know it fails on XIic_SelfTest This board is brand new, I only have it for a few weeks. I havent connected anything to the ports. I measured pins either with a tester or with a analog discovery so not short ciruits or similar have been produced. Any help would be apreciated. Edwin
  15. Hello, I'm trying to configure my Basys 3 board to control a DC motor through the Pmod connector with an HB5 within Vivado. I've followed all steps in the Pmod IP tutorial but I'm stuck at 3.3. I'm not sure which specific pmod ip block I should use or how exactly to connect it. I couldn't find one corresponding to the hb5. Any advice would be greatly appreciated. Additional points: I don't need clocks or interrupts fed to the pmod I'm simply trying to control the operation (on/off) of the motor through one of the on-board switches. Thanks, gd
  16. hassan_3md

    Filter using FIR compiler RFD is delayed

    I have build filter using FIR compiler. It is filtering the input quite well. I used COE generated from Matlab. I have two problems. 1- filter latency is 39 cycles. I am getting my RDY signal high after around 39 cycles. But RFD gets high after 251 cycles? I don't understand , if filter is giving me RDY signal high then according to FIR compiler datasheet figure of MAC multiplier timings, i should get RFD as soon as RDY gets high. I have tried both systolic and transpose MAC. I am attaching the figures from chip-scope. ZOOM-IN of ND-RFD ZOOM-IN of RDY ZOOM-OUT including two RFDs I want to get RFD as soon as my filter output is ready. Any clue ! 2.All is fine. filtering is good. I am using filter range from 900hz-3300hz. I am getting TICK like sound after some 500msec. I saw it on oscilloscope it is some type of clipped signal containing 5-6 cycles of not any specific frequency. the signal is looking more like square wave due to clipping. I am getting that TICK sound even if I did not attach LINE IN cable (from which data is fed to filter input through CODEC). But if I programmed the input of filter to '0' in verilog, I get nothing. Tick sound is also removed now . Filter is generating tick sound in any other condition, What is this? am I getting overflow some where? Thanks
  17. Hello. I am a beginner in FPGA. Also I am poor in English. Sorry. I am developing with Nexys Video. Although the design is complete, I am suffering from using QSPI Config and e-FUSE security together. I tried QSPI Config first. This worked well. Next I tried e-FUSE security. I wrote the security key and finished setting the FUSE register, After that, I could not program the QSPI. When executing the program, the following error will be displayed and will be aborted. -------------------------------------------------------------------- [Labtools 27-3165] End of startup status: LOW -------------------------------------------------------------------- You can not configure from QSPI, but you can configure an encrypted bit / bin file using JTAG. I replaced the USB cable with reference to the past forum, but there was no effect .... What does this error mean? Is there a solution for using QSPI Config and e-FUSE security together? Please tell me if you need information to solve the problem. Thank you koseki.
  18. We are suppose to add a library from here: https://github.com/Digilent/vivado-library/releases and add it to the projects IP repository list to be able to add the block in the IP Integrator. I have checked all the releases and i cant find the Pmod NIC100 anywhere, i think its called PmodNIC, but correct me if am wrong because i haven't seen it anywhere anyway. Until i find this IP, the Pmod is just another paperweight on my desk along with my stalled project, Please help. I am using the Arty A7: Artix-7 FPGA Development Board.
  19. Aleksandar

    USB CAM INTERFACING TO ZYBO

    Hello, my friends, i am new here and it is my first project. This project will be my BSC. I have to make next: 1. Make USB CAM interfacing on System Level using systemC... My diagrams are shown in the post. I need to capture the photo using a USB CAM. After that, the picture needs to be stored in some memory. After that the image processing logic (In my case, the logic needs to have the photo (stored in memory) as its input, the idea is just to decrease the photo size (pixels) and the output is the result (decreased size picture)), after that the result of processing needs to be stored in memory too. After that i have to choose... in easier way i will use some photo viewer to see the result, in more difficult way i will use HDMI in order to see my result on the HDMI enabled monitor. My plan is making it on System Level using coding, HLS,IP integrator, SDK for some software. 2.If SystemLevel work great i need to make it on RTL, IP level using pure HDL. I will use Vivado. I am not sure for now what i need to modify from SystemC to IP level (For now, i think just Image processing logic). 3.IP verification using QuestaSim. I have a question: 1. Has someone done something similar? Can you help me, like as give me some good literature or example (For now i am focusing on USB interfacing, i have been searching about this about few days, but without results..., I have read a book (SystemC "From Ground up")). 2. All suggestions are welcome Best regards!
  20. vinay_shenoy

    SD Mode Operation for PmodSD

    Hello, Does PmodSD (https://reference.digilentinc.com/reference/pmod/pmodsd/reference-manual) support SD mode of operation? Is it designed only to work with SPI mode as written in the reference manual? Please let me know Regards, Vinay Shenoy
  21. Hi All, I have recently downloaded Vivado 2018.2 and begun playing around with CMOD A7 35T. I did the the blinky tutorial and then just finished Cmod A7 Programming Guide. At the end of which, I programmed the button project into the flash memory of the device. I then disconnected the device and plugged it back in to verify the code was loaded onto the device on startup. The code indeed loaded and I can light the LEDs with the corresponding button; however, now my host pc cannot find the target device anymore. I tried restarting Vivado and plugging and unplugging the FPGA board and nothing seems to get it to show up in the hardware manager wizard or autoscan. I'm pretty new to FPGA programming so I could use some help to get my board reconnected and the program in Flash erased. Thanks
  22. I've coded UART receiver and transmitter separately in verilog and tested them on Basys 3 FPGA board with Tera Term terminal. I want to connect a USB Keyboard with the board and on pressing keys on keyboard, they gets reflected on Tera Term at same time. ToDo: Basys 3 Board receives data from keyboard and then transmits that data to elsewhere (say Tera Term terminal or a Pmod LCD screen) Problem:- Can anyone help me in how to use USB Keyboard with Basys 3 and how can I implement my UART in this. Attechments: UART receiver and transmitter code is attached below. UART_tx.v UART_Rx.v
  23. Hello, I am using Zed board 7000. I want to do Image Processing or basic computation in Zed board on PL side using FPGA. I was a bit confused to start either with a Linux image(PetaLinux or Xillinux) or directly through the Vivado software. Is it possible to do any computation or Image Processing on the PL side using ARM processor only to interface the peripherals(I don't want the computation to be done on the ARM processor). Kindly provide any reference link or tutorial which can address my queries. Thanks in advance. ---Nikith--
  24. Hi all, I am doing a project on vhdl in which i am trying to display a pattern (like forming an eight) on seven segment display on spartan 3 fpga kit.I have written the vhdl code and simulation works correctly,but the problem is i am not able to write the ucf code (written but may be wrong) required for implementation on spartan 3 kit.I would highly greatful if anyone can help me as to how to write ucf code or modify my vhdl code. Thanks in advance. Regards, Nikhil Singh pattern generator.txt
  25. Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.