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Found 6 results

  1. Hi, I'm relatively new to using Vivado with the Digilent boards. I have an Arty Z7-20 and started using it with Vivado 2019.1. I want to move on to Vivado 2020.1. When I originally installed 2019.1 I downloaded the Digilent vivado-library-v2019.1 from here https://github.com/Digilent/vivado-library/releases There does not seem to be a library v2020.1, v2019.1 seems to be the latest. Can I use library v2019.1 with Vivado 2020.1 or is there another way to achieve this? Thanks for your help!
  2. I'm working with ARTY-A7 FPGA board and ADEPT v2.19.2 in Windows 10. At first, the system often lost contact with the board, but after reinstalling digilent.adept.system_v2.19.2, the connection was restored. Now reinstalling no longer helps. What can be a reason?
  3. Hi, I am using Arty 7 to generate clock with different frequency. I wanted to save this data in my PC .since baud rate is 115200 and i am generating clock with 5MHZ ie at Rate of 5mbps. here speed of generation and data transfer are not same,speed of data transfer is much less than generation. please suggest me how can I save the data which i am genereting at same time.should I use ethernet for It?
  4. I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution. I know this has sort of been beaten to death...so take it easy on me. I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up. I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated. IP block in Vivado is customized as shown in image below. In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard. Bitstream generates succes
  5. Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.
  6. gsandy

    marsbar

    Vivado 2017.2 Windows 10 - I am a Vivado newbie I am trying to use the Arty board for some prototyping, I am trying to make my own new Block Design to instantiate in my new project, I grabbed the ethernet-lite reference design, I upgraded all IP. Added my new blocks, and generated. I am getting issues with the MIG, I checked the pinout of the symbols and it seems correct to match my axi_mem controller M0. I tried to re-customize the MIG_7series IP, the pinout seems correct against the reference design board.prj. . I checked the datasheet of the reference design and entered everythi