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Found 19 results

  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (, but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial ( The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation". When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal. I've attached my board file as both .bd and .png. Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial. But, it did not work. I'll walk you through what I did because there are a few things that I am confused about. Unless otherwise noted I followed the instructions exactly. Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything. Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial. I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr. Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3. One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4. Step 5: it doesn't work. Does anyone have any suggestions? Is the SPI Flash some sort of external hardware that I need to plug into the Arty? Thanks in advance.
  2. Hi, I'm working on ZYBO SoC. I want to boot it from QSPI flash but it fails anyhow. I have tried two methods using Vivado and IMPACT tool. 1. After successful implementation I created .bit and .bin files for a simple led_blinky project. Than I added "Configuration Memory Device" and selected Spansion s25fl128s 3.3v flash. I loaded the .bin file and then Erased, Verify and Programmed the flash step by step by checking the checkbox. The problem is with verify step. It fails every time. even then if I program it ignoring the failed verify step, it obliviously doesn't boots the program and no led blinks on board after resetting it. PS: I've taken care of the Jumpers already. 2. In the iMPACT tool I first created the PROM for a single FPGA, added 128MiB and created a .mcs file from the .bit file. then I initialized chain and after successful detection of board I added SPI Flash (which is attached above the ARM in the workspace figure) and loaded the flash with .mcs file. than I get option to either Erase, Verify or Program the flash. here too the program fails at Verify Step. Please help out.
  3. Hello Everyone, I am trying to get my Arty Z7-20 (XC7Z020) to boot from flash with encryption enabled. If I do not enable encryption, I am able to get this to work. I am using the tool "Create Boot Image" in the Xilinx SDK. I open the encryption tab and check the box labeled "Use Encryption" and provide the "Part name." The Part name I use is "XC7Z020." I have also tried "XC7Z020CLG400", which I found when using that board in a Vivado project. The Boot Image is created just fine, and I am able to program the flash. However, when I power on the FPGA, the done light does not come on and it seems to get stuck booting. I do have the jumper set to QSPI. Any idea why I am having this issue? Thanks, Christian
  4. Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws the following error: “This application requires a AXI Quad SPI in the hardware.” At this point, the ‘Next’ and ‘Finish’ buttons are greyed out, so I hit a dead-end. Could you please advise how I would go about storing this demo in SPI Flash? Many thanks in advance, Ben Cook
  5. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers Michael Betz
  6. Dean@L3

    CmodA7 flash size

    The CmodA7-35T uses a N25Q032 flash. This provides sufficient room for the bit file and a little less than half of it for something else like an elf load. If two bit loads were desired such as for a multi boot reconfiguration with a golden load and a field installed load there would not be sufficient room to do this. Perhaps compressing the bit files might be a way to still make that work. I was looking at this line of flash devices and noticed that there is a general trend toward the lower sizes becoming less available or obsolete and the cost for larger sizes aren't much more than the smaller ones now. In particular the 032 and 064 seem to be going away. With that, is there any plan to use larger size flash devices for this product in the future?
  7. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!
  8. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  9. Hi, I have a question, there is a way to programm my Cmod A7 without Vivado->Hardware Manager? I got some issues with Vivado, sometime crash. Another question is, there is a way to separate programming phases? At moment i have a download.bit, firmware.srec and data.txt, with hardware manager i have fused them in firmware.mcs and have flashed it in my SPI Flash. There is a way to program my flash only with download.bit and firmware.srec and later with data without overriding the other memory banks? Kind Regards Stefano
  10. 6HJS

    NEXYS 3 Parallel PCM

    Dear all, I bought a NEXYS 3 to evaluate the Parallel PCM on board (IC10). The schematic clearly indicates the IC10 is NP8P128A13T1760E phase change memory. However, the chip IC10 on the test board is showing it is RC28F128P33TF60 which is a SLC Flash, rather than PCM. Please tell me which chip is actually used on the NEXYS 3 Rev.B?
  11. i am a student. my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification) i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that. but the instruction is always 0x00000000 !! (i used chipscope to detect the signal) (i used startupe2 to access CCLK) it seems like i didn't access the flash, can anyone help me? thanks a lot !! pls save me....
  12. taaha

    data read write to flash

    Hi, I am using virtex 5 LX50T. I am developing some code in xilinx ise design suite. first i was storing some data in ddr2 but now i want to use flash to store some data as it stores data permanently. however only material i could find on the internet is related to EDK and microblaze. can you recommend me some link from where i can see how to store data within flash. Also, in virtex 5 reference manual, following line is written " A reference design on the Digilent website provides an example of driving the Flash memory " however i could not find a design on the website. Thankx in advance
  13. Hi, I'm new to FPGAs, so I purchased a BASYS3 to play around with. In following the "Getting Started with BASYS 3" video (youtube), I cannot save e a configuration to a memory device as that option is grayed out in my case (see attached screen capture). Does anyone have any ideas what's causing this and how to overcome it? Thanks in advance
  14. All: I've been incrementally developing both hardware (MicroBlaze with AXI peripherals) and software for the MicroBlaze itself. I've set up my software program size so that all software and hardware configuration can fit into a single .bit file. I've been able to program the flash several times, but yesterday have been getting errors while attempting to erase the flash. Notes are below. Is there a HW/SW program I could load onto the FPGA to prove or disprove that the flash is broken? Thanks!! Peter From the Vivado side: create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {n25q32-3.3v-spi-x1_x2_x4}] 0] set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.FILES [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]] set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] startgroup if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }; INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]] Mfg ID : 20 Memory Type : ba Memory Capacity : 16 Device ID 1 : 0 Device ID 2 : 0 Performing Erase Operation... Erase Operation failed. ERROR: [Labtools 27-3161] Flash Programming Unsuccessful ERROR: [Common 17-39] 'program_hw_cfgmem' failed due to earlier errors. From the XSDK side: bootgen -arch fpga -image \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/bootimage.bif \ -w -o \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/BOOT.bin \ -interface spi program_flash -f \ /home/pmeyer/WORK/DA-Test/ChameleonFPGA/UARTSlaveController/UARTSlaveController.sdk/top_hw_platform_0/cache/BOOT.bin \ -offset 0x00000000 -flash_type n25q32-3.3v-spi-x1_x2_x4 -blank_check -verify -cable type \ xilinx_tcf url TCP: ****** Xilinx Program Flash ****** Program Flash v2016.3 (64-bit) **** SW Build 1682563 on Mon Oct 10 19:07:26 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. Connecting to hw_server @ TCP: Connected to hw_server @ TCP: Available targets and devices: Target 0 : jsn-Cmod A7 - 35T-210328A2B5A8A Device 0: jsn-Cmod A7 - 35T-210328A2B5A8A-0362d093-0 Retrieving Flash info... Initialization done, programming the memory Performing Erase Operation... Erase Operation failed. ERROR: Flash Operation Failed Server disconnected during TCF command /home/pmeyer/3rdParty/SDK/2016.3/bin/loader: line 164: 20344 Segmentation faul
  15. mallesh

    Flashing genesys2 boards

    Hello, I would like to flash digilent genesys2 board with a project which uses microblaze and peripherals such as DDR and uart. This project is similar to user demo without display. Can you give me the instructions to build the flash file and program flash. I am new to FPGA domain and detailed instructions will be useful. I do see that the instructions for flashing firmware But this project does not have microblaze. Application on microblaze is a standalone application. Please let me know if you need any more information. Thanks, MH
  16. Hi, I have encountered a problem programming the flash of my CMOD A7 35T with the bootloader image, so that the FPGA would automatically configure itself after power on. Briefly, I placed my project (through its linker script) into the SRAM CELLS of the board and I programmed the flash with the SREC of the project. Now, if I program the FPGA with the bootloader elf (placed into the BRAMs), it works fine (the bootloader actually moves the program data from flash to the SRAM CELLS). But if I try to program the flash with the download.bit (created with "Program Flash" and the bootloader .elf) it doesn't do anything. I followed these guides: - - - I also created a .mcs file with both the download.bit (FPGA config file) and the project SREC) with this TCL command in Vivado: write_cfgmem -format mcs -size 4 -checksum FF -interface spix4 -loaddata "up 0x0 /path/to/download.bit up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test but it didn't work. I really need to write the FPGA config file toghether with the bootloader image to the flash. How can I solve this problem? Thank you in advance, Antonio Daril Crispino
  17. Hello, I'm a baby engineer. I want to write a binary user data file as well as a fpga configuration file in flash memory, Genesys2. I did it to Atlys board using a Adept software (you know It included the flash writing function!) in very easy way. But Genesys2, doesn't work. What can I do in order to write the user data to a desired start address like 0xA0000. in Vivado. or I just wait to the update Adept..?
  18. Hello. I am working with an Atlys board. I am trying to transfer a bitstream file and a linux image to the SPI flash. In windows I remember doing it from the flash tab in the Adept application. Now I am working on a linux computer and I've installed the Adept 2 runtime and utilities. I've read the man pages for the 3 utilities (dadutil, djtgcfg and dsumecfg) but it is still not clear to me if it is posible to transfer to SPI flash using these utilities. Is it?
  19. Hi all, I am new to fpga so need some help in selecting a board. I need a spartan 6 board which has an flash memory and can be programmed using a JTAG. not through usb jtag. can some one help me by listing all such boards ? Thanks in advance sarath