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Found 24 results

  1. Hello, I tried posting this on the Xilinx forums but got no response. These forums look more active and friendly so hopefully somebody can help me. I am really stuck. I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work. I am using an Artix-7 35T Arty FPGA Evaluation Kit. I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine. First, I created a simple "Hello World" program by follo
  2. Hi All, After I did a firmware update I can't auto-connect to my wifi. OpenScope v1.301.0 Written by: Keith Vogel, Digilent Inc. Copyright 2016 Digilent Inc. File Systems Initialized MRF24 Info -- DeviceType: 0x2 Rom Version: 0x31 Patch Version: 0xC USB+: 4703392uV VCC 3.3: 3297119uV VRef 3.0: 3000000uV VRef 1.5: 1501465uV USB-: -4662143uV Using calibration from: flash Unable to connect to WiFi AP. Error 0xA000001B Upon further investigation it appears I can't read/wite from flash anymore: Getting error trying to save calibration: Calibrating instr
  3. I'm trying to build a design for the Arty A7-100 (not using MicroBlaze), using the AXI Quad SPI memory for user data (and also for bitstream storage). The Reference Manual (and the master .xdc file) mention six external pins for this (actually the .xdc file only mentions five). But when I select the Arty A7100/External Memory/Quad SPI Flash from the "Board" window, it gives me a block for which the SPI_0 interface has 18 pins. Essentially each data pin has become three (_i, _o and _t). Am I supposed to put IO buffers there myself, or have I somehow got the wrong block? If so, please would
  4. Hi FPGA gurus ! Merry Christmas and happy new year to all of you FPGA lovers at Digilent ! I'm trying (unsuccessfully) to store Atlys HDMI demo to SPI/Flash so that whenever I turn the Atlys board on the project runs, without the need to upload and launch it through SDK. Atlys HDMI demo is a PLB based project and the only piece of info I can find about storing projects to SPI/Flash is for AXI based projects. Can anybody help me achieving this ? Any help would be greatly appreciated. Cheers
  5. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended o
  6. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able
  7. Hi, I'm working on ZYBO SoC. I want to boot it from QSPI flash but it fails anyhow. I have tried two methods using Vivado and IMPACT tool. 1. After successful implementation I created .bit and .bin files for a simple led_blinky project. Than I added "Configuration Memory Device" and selected Spansion s25fl128s 3.3v flash. I loaded the .bin file and then Erased, Verify and Programmed the flash step by step by checking the checkbox. The problem is with verify step. It fails every time. even then if I program it ignoring the failed verify step, it obliviously doesn't boots the pr
  8. Hello Everyone, I am trying to get my Arty Z7-20 (XC7Z020) to boot from flash with encryption enabled. If I do not enable encryption, I am able to get this to work. I am using the tool "Create Boot Image" in the Xilinx SDK. I open the encryption tab and check the box labeled "Use Encryption" and provide the "Part name." The Part name I use is "XC7Z020." I have also tried "XC7Z020CLG400", which I found when using that board in a Vivado project. The Boot Image is created just fine, and I am able to program the flash. However, when I power on the FPGA, the done light does
  9. Hello, I have a Nexys Video board and I have successfully loaded the “Nexys Video HDMI Demo”. I followed the tutorial "Using Digilent Github Demo Projects" to install and run the project through Vivado and SDK. I would like to learn how to get this demo to boot from QSPI flash following initial application of power to the board. I tried to follow this tutorial “How To Store Your SDK Project in SPI Flash". However, I get stuck creating the bootloader at step 1.2 as I do not have the option to use the ‘SREC SPI Bootloader’ template. When I try to select SREC SPI Bootloader, the SDK throws
  10. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers
  11. The CmodA7-35T uses a N25Q032 flash. This provides sufficient room for the bit file and a little less than half of it for something else like an elf load. If two bit loads were desired such as for a multi boot reconfiguration with a golden load and a field installed load there would not be sufficient room to do this. Perhaps compressing the bit files might be a way to still make that work. I was looking at this line of flash devices and noticed that there is a general trend toward the lower sizes becoming less available or obsolete and the cost for larger sizes aren't much more than t
  12. I have successfully used Vivado to store the bitstream into flash. On power-up, however, it does not program itself. If I push the PROG button, it does load the program from flash. That takes about 6 seconds. Two questions: 1. how do I get the program to auto-load? 2. how can I get it to load faster? the default program from Digilent loads in under a second. Thanks!
  13. Dear digilent, I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: https://reference.digilentinc.com/reference/pmod/pmodsf/start ( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F
  14. Hi, I have a question, there is a way to programm my Cmod A7 without Vivado->Hardware Manager? I got some issues with Vivado, sometime crash. Another question is, there is a way to separate programming phases? At moment i have a download.bit, firmware.srec and data.txt, with hardware manager i have fused them in firmware.mcs and have flashed it in my SPI Flash. There is a way to program my flash only with download.bit and firmware.srec and later with data without overriding the other memory banks? Kind Regards Stefano
  15. 6HJS

    NEXYS 3 Parallel PCM

    Dear all, I bought a NEXYS 3 to evaluate the Parallel PCM on board (IC10). The schematic clearly indicates the IC10 is NP8P128A13T1760E phase change memory. However, the chip IC10 on the test board is showing it is RC28F128P33TF60 which is a SLC Flash, rather than PCM. Please tell me which chip is actually used on the NEXYS 3 Rev.B?
  16. i am a student. my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification) i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that. but the instruction is always 0x00000000 !! (i used chipscope to detect the signal) (i used startupe2 to access CCLK) it seems like i didn't access the flash, can anyone help me? thanks a lot !! pls save me....
  17. Hi, I am using virtex 5 LX50T. I am developing some code in xilinx ise design suite. first i was storing some data in ddr2 but now i want to use flash to store some data as it stores data permanently. however only material i could find on the internet is related to EDK and microblaze. can you recommend me some link from where i can see how to store data within flash. Also, in virtex 5 reference manual, following line is written " A reference design on the Digilent website provides an example of driving the Flash memory " however i could not find a design on the website. Th
  18. Hi, I'm new to FPGAs, so I purchased a BASYS3 to play around with. In following the "Getting Started with BASYS 3" video (youtube), I cannot save e a configuration to a memory device as that option is grayed out in my case (see attached screen capture). Does anyone have any ideas what's causing this and how to overcome it? Thanks in advance
  19. All: I've been incrementally developing both hardware (MicroBlaze with AXI peripherals) and software for the MicroBlaze itself. I've set up my software program size so that all software and hardware configuration can fit into a single .bit file. I've been able to program the flash several times, but yesterday have been getting errors while attempting to erase the flash. Notes are below. Is there a HW/SW program I could load onto the FPGA to prove or disprove that the flash is broken? Thanks!! Peter From the Vivado side: create_hw_cfgmem -hw_device [lindex [
  20. Hello, I would like to flash digilent genesys2 board with a project which uses microblaze and peripherals such as DDR and uart. This project is similar to user demo without display. Can you give me the instructions to build the flash file and program flash. I am new to FPGA domain and detailed instructions will be useful. I do see that the instructions for flashing firmware https://reference.digilentinc.com/genesys2/pg. But this project does not have microblaze. Application on microblaze is a standalone application. Please let me know if you need any more in
  21. Hi, I have encountered a problem programming the flash of my CMOD A7 35T with the bootloader image, so that the FPGA would automatically configure itself after power on. Briefly, I placed my project (through its linker script) into the SRAM CELLS of the board and I programmed the flash with the SREC of the project. Now, if I program the FPGA with the bootloader elf (placed into the BRAMs), it works fine (the bootloader actually moves the program data from flash to the SRAM CELLS). But if I try to program the flash with the download.bit (created with "Program Flash" and the bootloader .el
  22. Hello, I'm a baby engineer. I want to write a binary user data file as well as a fpga configuration file in flash memory, Genesys2. I did it to Atlys board using a Adept software (you know It included the flash writing function!) in very easy way. But Genesys2, doesn't work. What can I do in order to write the user data to a desired start address like 0xA0000. in Vivado. or I just wait to the update Adept..?
  23. Hello. I am working with an Atlys board. I am trying to transfer a bitstream file and a linux image to the SPI flash. In windows I remember doing it from the flash tab in the Adept application. Now I am working on a linux computer and I've installed the Adept 2 runtime and utilities. I've read the man pages for the 3 utilities (dadutil, djtgcfg and dsumecfg) but it is still not clear to me if it is posible to transfer to SPI flash using these utilities. Is it?
  24. Hi all, I am new to fpga so need some help in selecting a board. I need a spartan 6 board which has an flash memory and can be programmed using a JTAG. not through usb jtag. can some one help me by listing all such boards ? Thanks in advance sarath