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Found 7 results

  1. I am trying to investigate how sparsity (the number of zeroes in the filter coefficients) affects the implementation of a filter on the FPGA. Specifically, I am interested in the number of BRAM blocks and DSP slices used for a sparse filter versus a non-sparse filter of the same length. I assume the filter coefficients to be symmetric and the number of taps to be odd. I have been experimenting with the FIR compiler GUI and have observed the following. For one output per cycle (No overclocking), The filter coefficients [1 2 3 4 0 1 2 3 4 ] use 9 DSP slices. Shouldn't this be 4 DSP slices (if we use the symmetry of the coefficients)? The filter coefficients [1 0 0 0 0 0 0 0 1] use 5 DSP slices. We have just the two multipliers here? Why do we need 5 DSP slices? For both of the filter coefficients, no BRAM units are used. When I increase the clock frequency, the number of DSP slices used goes down (although, I do not see a clean division here i.e. increasing the clock frequency by a factor of 2 does not reduce the DSP slices by half), but the number of BRAM units used increases. For example, the filter coefficients [1 2 3 4 0 1 2 3 4] use 6 DSP slices, (down from 9), and 5 BRAM blocks (previously 0 in the not overclocked case) when overclocked by a factor of 2. Similarly, overclocking by a factor of 3 reduces the number of DSP slices to 4, and the BRAM count goes to 3. Is there some relation between the number of DSP slices and the BRAM count? Note: I have also posted this question to Xilinx Forums, but have not received any feedback.
  2. I have build filter using FIR compiler. It is filtering the input quite well. I used COE generated from Matlab. I have two problems. 1- filter latency is 39 cycles. I am getting my RDY signal high after around 39 cycles. But RFD gets high after 251 cycles? I don't understand , if filter is giving me RDY signal high then according to FIR compiler datasheet figure of MAC multiplier timings, i should get RFD as soon as RDY gets high. I have tried both systolic and transpose MAC. I am attaching the figures from chip-scope. ZOOM-IN of ND-RFD ZOOM-IN of RDY ZOOM-OUT including two RFDs I want to get RFD as soon as my filter output is ready. Any clue ! 2.All is fine. filtering is good. I am using filter range from 900hz-3300hz. I am getting TICK like sound after some 500msec. I saw it on oscilloscope it is some type of clipped signal containing 5-6 cycles of not any specific frequency. the signal is looking more like square wave due to clipping. I am getting that TICK sound even if I did not attach LINE IN cable (from which data is fed to filter input through CODEC). But if I programmed the input of filter to '0' in verilog, I get nothing. Tick sound is also removed now . Filter is generating tick sound in any other condition, What is this? am I getting overflow some where? Thanks
  3. I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir compiler core directly gives you the decimated output without handling fitler delay so what should i do if want to handle this filter delay in xilinx Fir compiler core sequence Filter-downsample
  4. Good afternoon everyone, I was wondering if someone implements a filter in an FPGA in VHDL language, but that was designed and generated by the FILTER DESIGN HDL CODER tool (Matlab). To help me with some doubts. Thanks
  5. Hello, I am using a NEXYS 4 DDR and I am acquiring some data with the ADC that has this card, I want to implement a filter to eliminate the noise. Someone has an example in VHDL. Thank you.
  6. Hello everyone! Finally I end my degree final project and I obtain a good mark (9.4/10) I have been working on this project 1 year more less. Summarizing this project... This project is based on HDMI IN SDSoC project from digilent GitHub (you can read this in the readme in my GitHub). I have increased this project with a JPEG encoder, new image filters and plugin architecture to develop new filters without have to write in the internal code. In this link, you obtain all the files and you can read about my DFP. I'm sorry but the memory is in Spanish. This system have a good performance with the plugin architecture (38.82 FPS with 1920x1080 images). If you want to do somethig cool with this project, the next step would be put Linux OS. I have learned a lot in this forum! Thanks! Regards, Raúl.
  7. Question from the customer: Can you add a math channel which depends on more than one sample of the input channel. For example, applying a window function to calculate the average of the last 10 samples, FIR filtering, etc. Would also be nice to see some basic support for FIR and IIR filters in the oscilloscope math channels; Answers: For such purpose the Scope Logging tool can be used. The following script applies a filter to one channel data and saves it as reference channel. function doRef(ch, ref, fir){ var cfir = fir.length; {// normalize window area var vol = 0; fir.forEach(function(v){vol+=v;}); for(var i = 0; i < cfir; i++){ fir[i] = fir[i]/vol; } } ref.enable = true; // clone to have proper information (sample rate...) // save and restore offset value var voff = ref.Offset.value; ref.Clone(ch); ref.Offset.value = voff; // workaround to get all data not only visible one var sb = Scope.Time.Base.value; Scope.Time.Base.value = 1; var rg =; Scope.Time.Base.value = sb; var rgf = []; var crg = rg.length; var crg1 = crg-1; var cfir2 = round(cfir/2); for(var i = 0; i < crg; i++){ var v = 0; for(var j = 0; j < cfir; j++){ var ij = i+j-cfir2; if(ij<0) ij = 0; if(ij>=crg1) ij = crg1; v += rg[ij]*fir[j]; } rgf[i] = v; } = rgf; } // source store fir window doRef(Scope.Channel1, Scope.Ref1, [1,2,1]); doRef(Scope.Channel1, Scope.Ref2, [1,2,4,8,4,2,1]);