Search the Community

Showing results for tags 'filter'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Test and Measurement
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 7 results

  1. I am trying to investigate how sparsity (the number of zeroes in the filter coefficients) affects the implementation of a filter on the FPGA. Specifically, I am interested in the number of BRAM blocks and DSP slices used for a sparse filter versus a non-sparse filter of the same length. I assume the filter coefficients to be symmetric and the number of taps to be odd. I have been experimenting with the FIR compiler GUI and have observed the following. For one output per cycle (No overclocking), The filter coefficients [1 2 3 4 0 1 2 3 4 ] use 9 DSP slices. Shouldn't this be 4 DSP sl
  2. I have build filter using FIR compiler. It is filtering the input quite well. I used COE generated from Matlab. I have two problems. 1- filter latency is 39 cycles. I am getting my RDY signal high after around 39 cycles. But RFD gets high after 251 cycles? I don't understand , if filter is giving me RDY signal high then according to FIR compiler datasheet figure of MAC multiplier timings, i should get RFD as soon as RDY gets high. I have tried both systolic and transpose MAC. I am attaching the figures from chip-scope. ZOOM-IN of ND-RFD ZOOM-IN of RDY ZOOM-OUT
  3. I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir
  4. Good afternoon everyone, I was wondering if someone implements a filter in an FPGA in VHDL language, but that was designed and generated by the FILTER DESIGN HDL CODER tool (Matlab). To help me with some doubts. Thanks
  5. Hello, I am using a NEXYS 4 DDR and I am acquiring some data with the ADC that has this card, I want to implement a filter to eliminate the noise. Someone has an example in VHDL. Thank you.
  6. Hello everyone! Finally I end my degree final project and I obtain a good mark (9.4/10) I have been working on this project 1 year more less. Summarizing this project... This project is based on HDMI IN SDSoC project from digilent GitHub (you can read this in the readme in my GitHub). I have increased this project with a JPEG encoder, new image filters and plugin architecture to develop new filters without have to write in the internal code. In this link, you obtain all the files and you can read about my DFP. I'm sorry but the memory is in Spanish. This system
  7. Question from the customer: Can you add a math channel which depends on more than one sample of the input channel. For example, applying a window function to calculate the average of the last 10 samples, FIR filtering, etc. Would also be nice to see some basic support for FIR and IIR filters in the oscilloscope math channels; Answers: For such purpose the Scope Logging tool can be used. The following script applies a filter to one channel data and saves it as reference channel. function doRef(ch, ref, fir){ var cfir = fir.length; {// normalize wind