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Found 2 results

  1. Hello Digilent Forum! I have been able to run the Cmod A7 Out of Box Demo and export it to an SDK/Vitis project, then modify memorytest.c to write and read new data to and from the SRAM. What a great demo for getting started with the Cmod A7! However, I would like to configure the external memory controller (AXI EMC) block to use its individual ports -- without using the Cmod A7 board file and the "cellular_ram" port from the EMC_INTF pin of the EMC block. I created a new project that uses the xc7a35tcpg236-1 FPGA (not the board file), edited the constraints XDC file, and pinned out the EMC block to match the specs of the onboard ISSI IS61WV5128 SRAM; but it fails to generate a bitstream file successfully. I have also tried to setup tristate buffers (IOBUF) at the top level similar to the demo project's user_35t_wrapper.v file does, but no luck. Configuring the EMC signals (mem_dq_i, mem_dq_o, mem_dq_t, mem_dq_io) for a tristate buffer to interface with the SRAM's data lines seems to be the most confusing part. An image of what I "think" the EMC block should look like is attached. Any help interfacing the EMC block and SRAM correctly (without the board file) would be greatly appreciated. Thanks! Ian