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Found 2 results

  1. Just like this post here, my out of the box example's ethernet is not working. In trying to follow the guide. Changed link speed to 100 as it said. The echo server isn't working, keeps saying the link is up then down, and my computer keeps connecting then disconnecting. All within about a second, so I don't have nearly enough time to see if anything is working even when it is "connected". So then I tried the peripheral test project, and I got an "AxiEthernet: Rx fifo over run" on the "AxiEthernetSgDmaIntrExample". So I increased the rx buffer in the IP re-customization to the max 32KB, no luck. I added some outputs to try and debug it, added the Axi dma bd ring checks to the tx & rx buffers, both pass. The example also errors with "Length mismatch" as it is not receiving everything it sent. When I do a debug launch I don't get the fifo over run, so either a coincidence or something is acting up. I also have it printing out the lengths of the rx/tx, tx is 1014, rx varies as low as 60 and as high as 216 from what I've seen so far. All the other tests (ethernet dma, timer ctr, timer interrupt, axi intc) passed. When I try unplugging the ethernet cable it hangs on waiting for the bytes to come back which I suppose makes sense. I'll attach my xsa. I've been setting the programming mode to JTAG so as far as I know the builtin example is still sitting there on the QSPI for if I need it. I couldn't get the code to build with 2020.1 even after upgrading everything, so I can't try that as a fix. EDIT: managed to get the echo working by polling the BMSR register and waiting for the negotiation complete bit to be set design_1_wrapper.xsa
  2. Hi! I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications. Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded. However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide: axi_ethernetlite_0: [email protected] { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&microblaze_0_axi_intc>; interrupts = <1 0>; reg = <0x40e00000 0x10000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; axi_ethernetlite_0_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: [email protected] { device_type = "ethernet-phy"; reg = <0>; }; }; }; phy0 section was written by me, as it was not provided by dts creation utility for the SDK. dmesg output: xilinx_emaclite 40e00000.ethernet: Device Tree Probing xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus. xilinx_emaclite 40e00000.ethernet: error registering MDIO bus xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2 Relevant kernel config: CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=y CONFIG_PHYLIB=y CONFIG_DP83848_PHY=y CONFIG_XILINX_PHY=y eth0 interface appears, and ifconfig eth0 192.168.1.222 doesn't produce any error. However, no other host on the network can reach the ARTY nor viceversa, not by ping, nor by poking at any random port. Any ideas? Thanks!