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  1. Hi, I followed the instruction in https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start carefully to create the simple echo server with Nexys video board. The vivado version is 16.2. The Ethernet licence is evaluation version. After creating echo server application and run with SDK , it does not run as expected, the output is as follows: -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence
  2. Hi. I have a problem while trying lwIP Echo server wiht Zybo-Z7 I follow this tutorial faithfully https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start but I face with a problem This problem occurs for both connection through router and connection directly with my laptop or desktop I try with 3 PC and all of it shows same result. Google suggest me to configure ethernet to be 100Mbps half duplex with Fixed IP settings and it doesn't work. I double-check that I'm using correct MIO pin and fix the 1
  3. Can somebody help me to do ethernet communication between pc and my nexys 3 board, i didnt get any idea of using the ip core...
  4. Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills and progressively prototype benchmark/ Proof-of-Concept (PoC) demo applications using the full computational capacity of the Artix-7 XC7A200T. Could you please advise what would be the best data/peripheral connection options to achieve high t
  5. I setup my Nexys Video for the first time, and tried to setup an echo server using Vivado/SDK. I followed the following tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start When I go to generate a bitstream, I get the following error: [Common 17-69] Command Failed: This design contains one or more cells for which bitstream generation is not permitted: design_1_i/axi_ethernet_0_U0_mac_U0/tri_mode_ethernet_mac_i/bd_929b_mac_0_tri_mode_ethernet_mac_v9_0_12) If a new IP Core license was a
  6. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The
  7. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io whi
  8. Hello All, I am currently working on Nexys Video Ethernet. I want to transmit and recieve UDP packets between PC and Nexys Video FPGA . Is it possible to perform without Microblaze? How to send UDP Packets from PC to FPGA.?
  9. hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  10. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that th
  11. Hello: I am unable to get Ethernet interface to work on Genesys-2 in my design which is migrated from a Xilinx board. I have a Microblaze based design that I am trying to port to Genesys-2 Board. This design is working on Xilinx KC705 evaluation board which uses the same Kintex-7 FPGA as Genesys-2. On this design I have Ethernet interface, DDR3 Interface and some other peripherals. We are using Linux for this design. This design was originally developed by another company and was used for evaluating their chip. It was developed on Xilinx evaluation board KC705. This company does no
  12. hello, I need help with troubleshooting ethernet. when I use ifconfig, I get below information. eth0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 inet 192.168.1.103 netmask 255.255.255.0 broadcast 192.168.1.255 ether 00:0a:35:00:1e:53 txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 146 base 0xb000 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0
  13. Hi I am trying to develop Ethernet transmission with Zybo Z7-10. I tried to add ports like eth_txctl to xdc file, but there is a critical warning I can't understand. You can see pictures in attachments, the ports in my module, the ports I connect pin with, also the project settings. I don't understand why vivado gives my critical warning that the pin is not valid. If I try the ports eth_rxctl and connects it with pin D13, there would't be any warnings. I attached the schematic link as well, where I found the pins and port. I really don't get it, for example, th
  14. Fields

    Arty and Ethernet

    Greetings! I am working with an Arty FPGA board in a personal project that involves the use of a computer and Ethernet to control the FPGA. As a first step, I want to manage the leds by using the computer. Probably a good choice will be to use a Tera Term terminal and manage the state of the leds with sentences like that: · Led 3 state ON · Led 2 state ON · Led 1 state OFF · Led 0 state OFF The problem is that so far I have never connected the FPGA to the computer using Ethernet before. I know that the best way to manage an Et
  15. Hi, I just got nexys video and was going down the list of out-of-box demo at the bottom of its reference manual : https://reference.digilentinc.com/reference/programmable-logic/nexys-video/reference-manual When I connect the ethernet cable, ACT/LINK/USER LEDs blink for a bit, then LINK/USER blink in sync indefinitely, but there's no IP address displayed on OLED screen, just shows 0.0.0.0 I tried checking things on my router side (Netgear), but there is no indication of the device in its logs. Are there any way to confirm that the ethernet is working properly?
  16. Hi! I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications. Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded. However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide: axi_ethernetlite_0: [email protected] { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network";
  17. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  18. alonzo

    Zybo Ethernet example

    Hello, I have tried to build an Echo Server on Zybo using example from SDK. Because I could not find any hardware examples I followed this one for Arty: https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start I just customized it for Zybo and used Zynq instead of Microblaze. I uploaded the program on my Zybo but Echo server does not work because every time I try to communicate with it I get the timeout. I have read on this forum that it is possible to design Zynq processing system (with Ethernet enabled) as har
  19. Hello, Do you know if "Analog Shield: High-performance Add-on Board for the Arduino Uno" can also be used with "MCU Leonardo Ethernet 2 Arduino". Regards
  20. Hi, I am trying to run the lwIP echo server application project template from the Xilinx SDK on my PYNQ board. I have followed this tutorial for the Zybo FPGA board (which also contains the ZYNQ): https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start Everything works fine until the very last step, when I come to connect to the echo server using telnet. The PYNQ is telling my via serial comms that Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 So I followed
  21. anurag

    ethernet with cmod A7

    hello, i want to know whether or not it is possible to connect ethernet port to CMOD A7. as number of input output lines are restricted .if yes then how?
  22. Does anyone have the project for the initial project containing all peripheral interfacing?
  23. Hi, I'm trying the tutorial(https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start), but it doesn't work. I create a project in Vivado 2016.2 and SDK 2016.2. So, may I have the sample project in vivado and sdk 2016.2? Thanks, TM-san
  24. Hello, Need Help ASAP. I have a working code of FPGA (Altera DE2-115 ,cyclon-IV) for coin mining. Can I use that code on NetFPGA 1G CML for mining, if not what changes should I made in code? If yes, Then how can I connect it with Ethernet (PHY) of NetFPGA 1G CML? Will I need extra coding to connect it with Ethernet protocol? Thankx
  25. Hi, I am looking to implement the use of Ethernet port of the Zybo board without Zynq PS. I am using Windows OS and Vivado 2017.2. I have already implemented the Iwip echo server project. Is there any suggestions or guideline about the use of Ethernet port on Zybo without Zynq PS? Thank you in advance. BR ALI