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Showing results for tags 'ethernet phy'.
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Dear Team, We have established Ethernet communication on Arty-7 35 T for FPGA to PC (Transmission) and PC to FPGA (Reception). We have done RTL design without using micro-blaze and On system side we are using Visual studio for sending commands to FPGA using socket programming. We are facing following problems which are given below : FPGA to PC communication works perfectly for any IP address, but When we send command from socket for PC to FPGA communication, Ethernet on FPGA only listen to xxx.xxx.1.255 - broad cast IP. FPGA does not listen to any other value than 255. What could be reason behind this? Another problem we observed related to wire shark. While having Ethernet communication, If we close wire-shark, FPGA stops sending data. We are not able figure the main cause.
I get this error when running the ZYBO server demo on linux -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back Start PHY autonegotiation Waiting for PHY to complete autonegotiation. Auto negotiation error Phy setup error Assert due to phy setup failure I don't know what to do.