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Found 5 results

  1. Dear Team, We have established Ethernet communication on Arty-7 35 T for FPGA to PC (Transmission) and PC to FPGA (Reception). We have done RTL design without using micro-blaze and On system side we are using Visual studio for sending commands to FPGA using socket programming. We are facing following problems which are given below : FPGA to PC communication works perfectly for any IP address, but When we send command from socket for PC to FPGA communication, Ethernet on FPGA only listen to xxx.xxx.1.255 - broad cast IP. FPGA does not listen to any other value than 255. What could be reason behind this? Another problem we observed related to wire shark. While having Ethernet communication, If we close wire-shark, FPGA stops sending data. We are not able figure the main cause.
  2. hi i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip. my frame is:- constant udp_frameA :frame60:= (x"FF",x"FF",x"FF",x"FF", -- mac dest x"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- mac src x"08",x"00",x"45",x"00", -- IP header x"00",x"2E",x"00",x"00", x"00",x"00",x"40",x"11", x"7A",x"C0",x"00",x"00", -- IP src x"00",x"00",x"FF",x"FF", -- IP dest x"FF",x"FF",x"00",x"00", -- port src x"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A" x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41"); and i am getting same frame on simulation and chipScope but i am not getting this frame in proper order on Wireshark. Wireshark result attached with it. please find this attachment. please respond me as soon as possible.
  3. hii am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip.In this project i am facing the problem to getting the mac address of board (phy chip) to send the arp frame and udp frame.because i am manually framming the udp and arp frame fr in my code for which i need source mac address i.e mac address of fpga board (or marvell phy chip).please respond me as soon as possible. constant udp_frameA :frame60:=(x"FF",x"FF",x"FF",x"FF", -- mac destx"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- i want to know this source mac address.x"08",x"00",x"45",x"00", -- IP headerx"00",x"2E",x"00",x"00",x"00",x"00",x"40",x"11",x"7A",x"C0",x"00",x"00", -- IP srcx"00",x"00",x"FF",x"FF", -- IP destx"FF",x"FF",x"00",x"00", -- port srcx"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A"x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41");
  4. Hello All, I am a beginner in FPGA and to start with I want to sent the output of a 8 bit counter to the outside world through ethernet. My counter is working. Can anyone please send me any links or pdf or suggestions which can help me to send the data out of the FPGA through ethernet. Thanks James
  5. Hi , Myself trying to make Ethernet link up (without lwip) on Genesys Virtex5 Board. I generated EMAC0 wrapper with loop back from Xilinx Code Generator , modified ucf for board schematic. Reeceive link is working fine , i.e my board is able to receive I Gbps packets from PC and in chipscope pro , I could see packets loop backed on the TXD lines and PHY TX led is blinking but no packet is reaching PC . The problem , I assume may be the TXD line delays and PHY not getting proper data from FPGA . I don't have visibility to the TXD lines at PHY side . I tried out a couple of things thinking that the PHY may not be getting window to sample data properly. 1) GTXCLK is shifted at 90,180,260 PHASES using DCM ..No luck :-( 2) Drive strength of I/O reduced which can reduce EMI interference 3) Slew rate changed Nothing worked out ..So please help me out with some suggestions. Thanks & Regards, Supriya