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  1. I am interfacing between a USB IC (a FT2232H FTDI chip) and a EEPROM IC (a 93AA56BT). To make the FTDI chip recognizable by Xilinx tools I need licensed Digilent Serial Numbers. How can I get a licensed serial number file to enable a USB-JTAG FTDI interface? Are these licenses keyed specifically to your chips? How can I enable a JTAG-USB FTDI interface?
  2. When I try to program my board after I generated the .bit/.bin files, i get the following error [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121]Check to make sure the cable targets connected to this machine are properly connectedand powered up, then use the disconnect_hw_server and connect_hw_server commandsto re-register the hardware targets.it says no hardware exists on the server, even though my board is plugged in with the mode jumper in the JTAG position. I also tried reinstalling Vivado to make sure the cable drivers were installed.
  3. Hi Everyone! I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the
  4. We have a board that uses the JTAG-SMT2 module to interface a Xilinx Zynq device. Most modules work without any issues, however one refuses to connect to the Zynq device. When first plugged into a computer (reproduced on 3 separate systems), it installs the FTDI driver for ‘USB serial converter’ properly. The misbehaving module installs an additional COM port driver and shows up as COMx. All the other working modules don’t install the COM driver. Disabling the VCP option did not make a difference. Version of the FTDI driver is 2.12 but also 2.10 and 2.8 did not seem to work. Is there any setti
  5. Hello, I am currently following the first tutorial of the Zynq Book using the Zybo board and I am t the part where I am to launch the SDK after exporting hardware and receive the following error after the SDK loads up: 'Importing Hardware Specification' has encountered a problem. An internal error occurred during: "Importing Hardware Specification". java.lang.NullPointerException. Attached is a screenshot of the error. Thank you for any help.
  6. Hello, I have Vivado 2014.4 installed on Ubuntu 12.04 (64bits). I have a Nexys 4 Digilent Board (Artix 7) connected to the PC through a USB cable but in the Hardware session I'm unable to connect to target. I get this error message: WARNING: [Labtoolstcl 44-26] No hardware targets exist on the server [localhost] Check to make sure the cable targets connected to this machine are properly connected and powered up, then use the disconnect_hw_server and connect_hw_server commands to re-register the hardware targets. Running the lsusb command in a terminal, the USB-UART IC of the board seems to
  7. Lara, is the Zybo Image Processing from sources tutorial ready? loved the Quick Start Test Demo and Github archive: you say: "We'll go into building these into a later tutorial," I'd particularly welcome a barebones git, as the current one is rather bulky! many thanks Jonathan
  8. I just received a new WF32 and I'm excited to hit the ground running... if I could get to Hello World. I'm using Arduino IDEs for several AVR boards, Edison, etc. and they're working fine on this system (MacBookPro w/ 10.9.5), so I'm comfortable that system, drivers, cables, etc. are OK. I'm using MPIDE 0150. Board and serial port are set. The board is acting like it doesn't have a boot loader. How should it normally behave on power-up from factory, or on reset? On power-up, I see 2 strong TX/RX pulse cycles on LD1/2, then nothing. Trying to load a sketch sees an occasional weak puls
  9. Hi, I downloaded the ZYBO PCB schematic file ZYBO_sch_B_V2.pdf from the link http://www.digilentinc.com/Data/Products/ZYBO/ZYBO_sch_B_V2.pdf This document is incomplete. For example, try finding IC17 or J11. Where can I find the complete schematic for my eval board (Rev ? Cheers, David
  10. Hi, I just got the JTAG-USB adapter and I've installed the adept runtime and tools. I don't see executables in what was installed: nothing under a bin directory. Where are the executables for the adept suite? The one page "reference manual" for the JTAG-USB should include a couple of lines showing how to launch the executables that talk to the device, IMO. That might be true for the other JTAG interface products. Thanks, Chris
  11. Hello! I'm planning to use a JTAG HS2 cable for custom SPI communication. Before I take the plunge and get the cables, I have a few questions: 1) is this cable based on the Digilent chip or the FTDI chip? 2) does the the Adept API work with Qt5 running in Cygwin on Windows7? Has anyone tried this? 3) has anyone tried using libusb to talk to the cable instead of using the Adept SDK? Thanks!
  12. Hi All, I am unable to read the registers on the Audio Code (SSM2603) on the Zybo board. I have followed all the example code I can find (Zybo_base_system). I have built the hardware in Vivado and it all builds with no errors. In Xilinx SDK I then create a modified C program using the code "audio_demo.c" as a reference. The C code compiles with no errors and I load the hardware and software on the Zybo. I then use an external logic analyzer to probe the i2c signal to verify it. All the write signals match up with the i2c format outlined in the Audio Code (SSM2603) datasheet. No errors are repo
  13. It does not appear that the 30MHz maximum speed for this device is operating, and or configured correctly when downloading an elf file Ubuntu $ xmd XMD% connect mb mdm -cable frequency 30000000 XMD% dow myFile.elf the download time is identical whether frequency is set from a low number 125000 to a high number 30000000 also attempted: XMD% fpga_isconfigured -cable frequency 30000000 ... FPGA is configured Is there an XMD command to show the "current" frequency?
  14. Jay

    Nexys Video + Camera

    Hi, I have used Atlys + VmodCam for probing camera enhancement algorithms. This time, upgrading to Nexys Video + Camera is needed due to the termination of Atlys. Is there any suggestion for what kind of camera module is the best in the market? Jay
  15. I have an application where I need to synchronize multiple components (boards and test equipment) with a single common clock or a common reference. I assumed this would be straight-forward with the Atlys board I have but seem to be mistaken. Are there no PMOD modules or VHDCI modules that provide access to the clock inputs (GCLK) on the FPGA? Preferably I'd like to run a coax cable, SMA, BNC, with LVTTL levels either a high speed clock or a reference that could then be multiplied up with-in the FPGA's DCMs. Looking though the PMODs and the VHDCI modules that doesn't seem to be a ready opti
  16. Hey guys! I followed the ''Embedded Linux hands-on tutorial'' to build and run Linux on my ZYBO board. I am trying to use the Ethernet but it seems does not work correctly. Here are some informations: I connect the board and my PC (ip adr: 169.254.29.208). When I ping ZYBO from my PC I got "Destination host unreachable" and "request timed out". When I ping PC from ZYBO I got "sendto: Network is unreachable". I'm using Vivado 2014.2 under Ubuntu 14.04 and didn't do any changes in addition to the tutorial. So anyone can help me with this? Thanks a lot! Best regards, JImmy
  17. Dear Community. I've recently bought a Zybo Zynq board and i'm having some getting started problems. Im known with both C and VHDL programming before but i've never had such a multi-purpose FGPA, dualcore board before. I tried following some basic tutorials, like: https://reference.digilentinc.com/zybo:gsg http://www.zynqbook.com/ and several youtube led blinks. But I'm experiencing different problems with all of them. My board isnt listed in the Vivado 2015 > new project > boards list I can't find the right settings to get the leds to the GPIO Or when I find a "pre made tutorial led bl
  18. I can't get the example in the Arty Programming Guide to work https://reference.digilentinc.com/arty:pg I even downgraded to Vivado 2015.1, but I still get critical errors from the XDC file. The part is correctly defined as an xc7a35tcpg236-1 [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [C:/Users/mlewis/Xilinx/Arty/project_1/project_1.srcs/constrs_1/imports/arty_master/Arty_sw_btn_Demo.xdc:15] Resolution: Verify the location constraints for differential ports are correctly specified in your constraints. The Site type should be of form: IO_LxxP for P-sid
  19. I am working with the Block Design flow in Vivado 2015.3. I don't seem to be getting how to connect the reset system. My design keeps acting like the clock is being held in reset. When I look closely it appears that the reset signal on the Arty is active low while the reset module in the design expects active high. What am I missing here? Michael Harpe
  20. Hi all, I am working on a project where the plan is that I will interface a camera module to the ZYBO for testing a few algorithms in HW. The problem I just noticed is, though the ZYBO says it supports "LVDS", it has 3.3v on the BANKs where the high speed PMOD goes. Is it still possible to use it for LVDS input? I have 4x 340 MBit/s LVDS pairs with 2 clock + 2 data coming from 2 cameras. I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination? The second thing I cannot find is if the LVDS pairs on the ZYBO that goes to a connector are
  21. Hi all, I am currently working on a video processing project and need to store frames of RGB signals into the DDR on the Zybo board. But it seems there is not many documents discussing how to use it. Here are the material I have read: 1) Zybo reference manual (doesn't cover much but mentions to read Zynq-7000 manual) 2) Chapter-10 of Zynq-7000 manual DDR memory controller ( focus a lot on the architecture, but not on how to use it) 3) The Zynq Book Tutorial (mentions DDR while introducing processing system) Can someone give me more directions on how to use t
  22. After doing the hands on linux tutorial for the Zybo I have some grasp on how to access custom IP in linx. However, I'm confused on how to access the three other registers that the IP core has in the demo. I know its using a file transaction to get the user data and write the data to the IP core register in the kernel space. Would I have to modify the kernel module source to parse the message and then do an IO write to a indicated register or do I have to write enough data to get to the desired register? Also how would I go about reading specific registers using the procfs method? (i.e. I want
  23. Hi, I'm looking at the schematics for the Arty board (considering purchasing one) and am wondering what power sequencing strategy it uses. It looks to me like there's no control over when voltages ramp up. Don't FPGAs have stringent requirements on bringing up the power rails? Thanks, Michael
  24. vport

    nexys2 fpga board usb

    I want to nexys2 board for usb communication. I have complete work on EPP usb communication now i want to use slave fifo on nexys2 board .i have some questions 1) Is nexys2 capable of slave ffio mode 2) how to disable EPP mode on nexys2 3) if there an eaxmple for nexys2 slave fifo so please give me lin thanks
  25. Hi, I'm using the ChipKit Wi-Fire board where I use an external ADC to capture data and transmit it over the SPI channel based on the Timer2 interrupt. Getting the Timer2 interrupt and ADC capture to work independently is no problem, it's only when I combine them together that something halts in an odd way. Below is my code, and basically, for testing purposes, I sample 50 samples, after which the Timer2 is disabled and I print out the numbers on the serial monitor. In the interrupt routine I set an interrupt flag, which will be caught in the main loop. /* CS: pin 10 MOSI: pin 11 MISO: pin