Search the Community

Showing results for tags 'errors'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions


  • Community Calendar

Found 2 results

  1. When trying to run the Digilent bsd project for Arty, Vivado 2015.4 cannot run Bitgen due to 2 critical warnings. I have been able to run the Digilent Xadc_Demo and GPIO projects successfully with no problems. I'm wondering if there is an error in the .tcl script for the bsd project. I've attached the Vivado critical warning messages. I'm new to both VIvado and Arty so I would appreciate help.
  2. Hi, I'm following an EE class where we are using your Real Analog - Circuits 1 textbook and lectures. I've been very pleased so far, but I happened to notice a giant bummer in chapter 4, section 6 - Maximum Power Transfer. The whole chapter is based on the misunderstanding that maximum power transfer also implies maximum efficiency, which is obviously wrong. A few qoutes: All of these claims only hold for Rload < Rsource, whereas Rload > Rsource will lead to higher efficiency and less power dissipated in the supply. I believe there are more cases of this misunderstanding appearing in the text, those are just a few examples. Regards, Marcel