Search the Community

Showing results for tags 'error'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 21 results

  1. I have been following your "low_level_zmod_adc_dac" demo tutorial found at, and I believe there may be a typo. I copied the TCL commands to check out the project and received a "couldn't read file" error in the TCL command window. The command provided in the demo tutorial is set argv ""; source digilent-vivado-scripts/digilent-vivado-checkout.tcl, with all hypens. However, the scripts from the GIT digilent-vivado-scripts GIT project use underscores in the tcl filenames. Note that the exa
  2. Hello, I am having issues with my analog discovery 2. When I try accessing the device in the device manager of waveforms, I keep getting the same error code listed below. I have tried redownloading the waveforms software, but this hasn't fixed the issue. Any help would be greatly appreciated. Thanks for the help!
  3. Hello, I need help on a Basys2 board, that show incompresible characters when Adept runs at begin. Then I get this when it Initialize Chain (see below). You can see the error on attached file. The board is from an school laboratory and it is use by many students, so nobody know what happend to get this status in the board. ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.19 Adept Application Rev 2.4.2 Copyright © 2010 Loading board information... Initializing Scan Chain... Board information loaded. Found device ID: ffffffff Found device I
  4. I purchased a PMOD-BT2 recently and since (according to your documentation) the SPI connector uses the same power as the regular PMOD connector, I though I could just connect it via the SPI header (not supplied), for programming. Strangely enough, the FPGA board (a Nexys4-DDR) would not power up. An investigation reveals a strange fact: according to an ohm-meter the power on the SPI header is reversed compared to your documentation. I would appreciate it if someone from Digilent could confirm this from the PCB schematics and update your documentation ASAP, as well as issue an errata, because c
  5. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into t
  6. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When lo
  7. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw
  8. Hi @Commanderfranz, How to solve this error: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: ddr3_sdram_0_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and sys_clock (LVCMOS33, requiring VCCO=3.300) Any comments I will appreciate it. thanks
  9. Hello, I ordered a brand new Analog Discovery bundle directly from Digilent a few weeks ago for use in a college class, but every time I have attempted to build a simple circuit and connect the board to WaveForms, I consistently get one of the two attached errors. The components of the parts kit have been working fine but it seems like there is a problem with the amount of power being supplied to the Analog Discovery board itself. Any help would be greatly appreciated. Thanks, bucklc2
  10. Hi, I have purchased the Multi-Touch Display Shield, see link below for actual model. I have downloaded the Arduino IDE folder, installed the mtds & MyDisp libraries and followed the QuickStart.txt. When I open an example from either of those libraries and attempt to compile, it fails and lists loads of errors (Please see .txt file attached where I have copied error messages). I have my Arduino Uno selected and the libraries installed, there are errors in the followings directories: \Arduino\l
  11. Hi, In the Protocol tool, the UART tab The ´Receive to File´ and ´Save´ button generate a windows error by me. Thanks in advance, Hans
  12. I'm getting these errors when trying to run synthesis a demo project from the arty resource page. On that page I tired doing the XADC. i did get it to generate the .tlc file stuff to make the project I did download the board files for the arty and placed them in the boards_files directory. but maybe it's not implemented correctly or im missing something. Some xilinx forums said to click on the "open block design" to fix this but mine is grayed out and I can't select it. Most tutorials online show the old Vivado UI the 2017.1 seems to be slightly different. mostly likely due to the missing
  13. Hi, I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it. EDIT: I have found three errors but do not know what they mean. [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IO
  14. Hello I installed the newest Vivado 2016.2 and the newest Zybo board files from git repo. Any attemp to build the project ends with multiple Warnings during the place phase, saying that some Mio ports have more than one voltage standard. And the placement never ends. It happens even when I try the simplest BD with Zyng core and two AXI_GPIOs for leds and buttons. any idea?
  15. Hello I am using AXI_dynclk and rgb2dvi from Digilentic git. The ref clock od dynclk core comes to AXI_clk pin. When placing the design, I will always get this critical warning for each generated clock. And the design says Completed but timing constraints not met. How can I fix this?
  16. Dear Sir, I am facing problem in getting license for Vivado Design Suite I have vouchers with written code on it found in FPGA kintex-7 box, but when we follow procedure by applying online it gives error of failure in export compliance verification I tried from different account and from different locations but error remained same. The Error is "We cannot fulfill your request as your account has failed export compliance verification. Please visit for a possible solution to resolve this error. "
  17. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compi
  18. I am using Ubuntu 14.04 and VIVADO 2014.4. I am trying to boot Linux on a zybo (7000)board, I tried to generate a bit stream and it is showing that the synthesis is failed. I have also attached a file. I also have a voucher from the digilent and used to generate a license file .lic. I opened the license manager many times and showed the license path and it said that the license was successfully installed.
  19. I followed the tutorial on Youtube shown below to 9:33 but my Bitstream generation is unsuccessful. I get the following rule violation: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs: btnD (LVCMOS18, requiring VCCO=1.800) and led[0] (LVCMOS33, requiring VCCO=3.300) Does anybody what I can do to fix it? Thank you very much! Tony
  20. Hello Guys! I hope you can help me with some doubts. I have a code that I use the ADC, TIMER and ETHERNET modules, when I try to compile it some erros are reported, as follows: C:/Users/MyName/Desktop/mpide-0023-windows-20140821/hardware/pic32/compiler/pic32-tools/bin/../lib/gcc/pic32mx/4.5.2/../../../../pic32mx/bin/ld.exe: small-data section exceeds 64KB; lower small-data size limit (see option -G) chipKITEthernet\utility\DNS.c.o: In function `DNSEndUsage': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:208:(.text.DNSEndUsage+0x0): relocation truncated to fit: R_MIP
  21. Hutch07

    NI Visa

    I have an error about not finding Visa or one of its components. Is Visa an add on?? I also do not have the option to select the correct COM port. I can see the Digilent 32WF connected to com 7. Any advice?