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Found 18 results

  1. I purchased a PMOD-BT2 recently and since (according to your documentation) the SPI connector uses the same power as the regular PMOD connector, I though I could just connect it via the SPI header (not supplied), for programming. Strangely enough, the FPGA board (a Nexys4-DDR) would not power up. An investigation reveals a strange fact: according to an ohm-meter the power on the SPI header is reversed compared to your documentation. I would appreciate it if someone from Digilent could confirm this from the PCB schematics and update your documentation ASAP, as well as issue an errata, because connecting the power the wrong way round has a habit of blowing things up.
  2. I am trying to operate the Nexys Video development board using the vivado hardware manager on a windows 8 system. However I keep getting No hardware targets exist on the server error. Steps i have taken to remedy the situation include: Re-installed Vivado with included cable drivers Tried different versions of vivado Tried on a different PC Formatted PC and installed vivado Updated FTDI drivers Tried 3 different (new) USB cables Installed cable drivers manually The programming jumper is in the right position (jtag), the USB cable is plugged into the correct (prog) port and the board is powered. Can anyone suggest anything else I might try to fix the issue? Thanks.
  3. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  4. Hi All: I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get. The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems. The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0]. 1. I added in the additional input - input [1:0] sw 2. I added in the case statement (which is currently commented out) 3. I commented out the original assignment of led - //assign led = clkdiv[26]; The problem crops up immediately with a Verilog error showing on the following line: case(sw) - The error states: Error: 'sw' is not a constant I've spent hours trying various changes...all to no avail. HELP....PLEASE!!!! Thanks Tons! VERILOG MODULE: module clk_divider( input clk, input rst, input [1:0] sw, output led ); wire [26:0] din; wire [26:0] clkdiv; dff dff_inst ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for (i = 1; i < 27; i=i+1) begin : dff_gen_label dff dff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din), .Q(clkdiv) ); end endgenerate assign din = ~clkdiv; /* begin case(sw) 2'b00: assign led = clkdiv[26]; 2'b01: assign led = clkdiv[25]; 2'b10: assign led = clkdiv[24]; 2'b11: assign led = clkdiv[23]; default: assign led = clkdiv[26]; endcase end */ assign led = clkdiv[26]; endmodule
  5. Hi @Commanderfranz, How to solve this error: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: ddr3_sdram_0_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and sys_clock (LVCMOS33, requiring VCCO=3.300) Any comments I will appreciate it. thanks
  6. Hello, I ordered a brand new Analog Discovery bundle directly from Digilent a few weeks ago for use in a college class, but every time I have attempted to build a simple circuit and connect the board to WaveForms, I consistently get one of the two attached errors. The components of the parts kit have been working fine but it seems like there is a problem with the amount of power being supplied to the Analog Discovery board itself. Any help would be greatly appreciated. Thanks, bucklc2
  7. Hi, I have purchased the Multi-Touch Display Shield, see link below for actual model. https://reference.digilentinc.com/reference/add-ons/mtdshield/start I have downloaded the Arduino IDE folder, installed the mtds & MyDisp libraries and followed the QuickStart.txt. When I open an example from either of those libraries and attempt to compile, it fails and lists loads of errors (Please see .txt file attached where I have copied error messages). I have my Arduino Uno selected and the libraries installed, there are errors in the followings directories: \Arduino\libraries\MyDisp\Examples\MyDispDemo\MyDispDemo1\MyDispDemo1.pde \Arduino\libraries\mtds\MtdsCore.cpp \Arduino\libraries\mtds\MtdsFs.cpp \Arduino\libraries\mtds\MtdsHal.cpp Does anyone know what is causing this, I have tried both Arduino 1.6.9 & 1.8.5 but it shows the same errors. Any help would be appreciated. Thanks, Evan Error compiling for board ArduinoGenuino Uno - Error Message.txt
  8. HansV

    Protocol

    Hi, In the Protocol tool, the UART tab The ´Receive to File´ and ´Save´ button generate a windows error by me. Thanks in advance, Hans
  9. I'm getting these errors when trying to run synthesis a demo project from the arty resource page. On that page I tired doing the XADC. i did get it to generate the .tlc file stuff to make the project I did download the board files for the arty and placed them in the boards_files directory. but maybe it's not implemented correctly or im missing something. Some xilinx forums said to click on the "open block design" to fix this but mine is grayed out and I can't select it. Most tutorials online show the old Vivado UI the 2017.1 seems to be slightly different. mostly likely due to the missing xadc_wiz_0 module but it shows up on the source list. Or maybe its a compatibility issue between Vivado 2016.4 and 2017.4 I'll wait for a response before trying something else.
  10. Hi, I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it. EDIT: I have found three errors but do not know what they mean. [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. bitstream_report.txt
  11. Hello I installed the newest Vivado 2016.2 and the newest Zybo board files from git repo. Any attemp to build the project ends with multiple Warnings during the place phase, saying that some Mio ports have more than one voltage standard. And the placement never ends. It happens even when I try the simplest BD with Zyng core and two AXI_GPIOs for leds and buttons. any idea?
  12. Hello I am using AXI_dynclk and rgb2dvi from Digilentic git. The ref clock od dynclk core comes to AXI_clk pin. When placing the design, I will always get this critical warning for each generated clock. And the design says Completed but timing constraints not met. How can I fix this?
  13. Dear Sir, I am facing problem in getting license for Vivado Design Suite I have vouchers with written code on it found in FPGA kintex-7 box, but when we follow procedure by applying online it gives error of failure in export compliance verification I tried from different account and from different locations but error remained same. The Error is "We cannot fulfill your request as your account has failed export compliance verification. Please visit http://www.xilinx.com/support/answers/44043.html for a possible solution to resolve this error. "
  14. Hello, I just recently bought a zybo board and was following the digilent tutorial and almost finished the getting started project. However, I cannot make the helloworld.c file after launching the SDK. I can still program the PL side, but if I cannot utilize the PS side. SO now I basically have a standard FPGA until I can get this issue resolved. I have been looking through the xilinx forums too and haven't seen a good solution to this problem. here is an example of the console output and a screenshot of the error message that pops up Building file: ../src/helloworld.c Invoking: ARM gcc compiler arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../getting_started_with_ZYBO_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.d" -o "src/helloworld.o" "../src/helloworld.c" make: *** [src/helloworld.o] Error -1073741502
  15. I am using Ubuntu 14.04 and VIVADO 2014.4. I am trying to boot Linux on a zybo (7000)board, I tried to generate a bit stream and it is showing that the synthesis is failed. I have also attached a file. I also have a voucher from the digilent and used to generate a license file .lic. I opened the license manager many times and showed the license path and it said that the license was successfully installed.
  16. I followed the tutorial on Youtube shown below to 9:33 but my Bitstream generation is unsuccessful. I get the following rule violation: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs: btnD (LVCMOS18, requiring VCCO=1.800) and led[0] (LVCMOS33, requiring VCCO=3.300) Does anybody what I can do to fix it? Thank you very much! Tony
  17. Hello Guys! I hope you can help me with some doubts. I have a code that I use the ADC, TIMER and ETHERNET modules, when I try to compile it some erros are reported, as follows: C:/Users/MyName/Desktop/mpide-0023-windows-20140821/hardware/pic32/compiler/pic32-tools/bin/../lib/gcc/pic32mx/4.5.2/../../../../pic32mx/bin/ld.exe: small-data section exceeds 64KB; lower small-data size limit (see option -G) chipKITEthernet\utility\DNS.c.o: In function `DNSEndUsage': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:208:(.text.DNSEndUsage+0x0): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:211:(.text.DNSEndUsage+0x20): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:213:(.text.DNSEndUsage+0x38): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' chipKITEthernet\utility\DNS.c.o: In function `DNSResolve': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:262:(.text.DNSResolve+0x48): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:256:(.text.DNSResolve+0x74): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' chipKITEthernet\utility\DNS.c.o: In function `DNSIsResolved': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:358:(.text.DNSIsResolved+0x0): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:369:(.text.DNSIsResolved+0xac): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:380:(.text.DNSIsResolved+0xfc): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:384:(.text.DNSIsResolved+0x114): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:388:(.text.DNSIsResolved+0x124): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:423:(.text.DNSIsResolved+0x1f4): additional relocation overflows omitted from the output collect2: ld returned 1 exit status I'm using the timer with interruption enabled, the ADC is used to scan 6 chs and the Ethernet to send the data to my computer, somebody coud help me? Regards.
  18. Hutch07

    NI Visa

    I have an error about not finding Visa or one of its components. Is Visa an add on?? I also do not have the option to select the correct COM port. I can see the Digilent 32WF connected to com 7. Any advice?