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Found 5 results

  1. Hello Everyone, I am trying to get Arty Z7-20 boot from flash with encryption enabled. I am following Xilinx 'XAPP1319' to program AES key to BBRAM. I created MCS boot image with 'fsbl' and 'program_aes_key_bbram' application program(xilskey 6.3 example 'xilskey_bbram_example' for Zynq not ZynqMP) for qspi flash as described in Xilinx 'XAPP1319'. However on booting from SPI flash, BBRAM example print exit message 'BBRAM Example failed' on serial console. On debugging with JTAG, I found it fails while programming BBRAM, in function I have the jumper set to QSPI while booting from flash. Attached is serial console output. Any idea why I am having this issue? bbram_out.txt
  2. Hello Everyone, I am trying to get my Arty Z7-20 (XC7Z020) to boot from flash with encryption enabled. If I do not enable encryption, I am able to get this to work. I am using the tool "Create Boot Image" in the Xilinx SDK. I open the encryption tab and check the box labeled "Use Encryption" and provide the "Part name." The Part name I use is "XC7Z020." I have also tried "XC7Z020CLG400", which I found when using that board in a Vivado project. The Boot Image is created just fine, and I am able to program the flash. However, when I power on the FPGA, the done light does not come on and it seems to get stuck booting. I do have the jumper set to QSPI. Any idea why I am having this issue? Thanks, Christian
  3. For bitstream encryption using battery-backed RAM, you are suppose to supply the Vccaux pin with voltage to keep the encryption key alive in memory. 1. Where is the Vccaux pin on the Cmod A7? (Hopefully it is not the VU pin because it would be really wasteful to power the whole FPGA just to keep the encryption key alive!) 2. What voltage is supposed to be supplied? Thanks, David
  4. Bruce

    Genesys Encrytpion

    Has anyone been able to load an encrypted mcs file on the Virtex 5 based Gensys? I can encrypt the bit file and load it directly and the board boots (of course once I load the encryption key.) However, when I load the MCS file the board doesn't boot, and a scan of the device status in Impact shows CRC error.
  5. Professors and researchers from University of Houston make use of Zedboard and Xilinx Vivado High Level Synthesisto implement the data encryption in the cloud computing. They explained this concept in two different conferences Field Programmable Logic (FPL) 2014 - Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGAs http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927414 IEEE Cloud 2014 - PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6973752&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F6968679%2F6973706%2F06973752.pdf%3Farnumber%3D6973752 The project is also sponsored by NATO. http://www.uh.edu/news-events/stories/2016/March/032316ShiNATO