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Found 5 results

  1. I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else. I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there. For making the connections, I've followed the schematic in the reference manual. I'm posting my top level design and I'm also attaching the constraint
  2. Hey Digilent, I've successfully run the low_level_zmod_adc_dac demo on my board with a ADC and DAC ZMOD. https://reference.digilentinc.com/reference/programmable-logic/eclypse-z7/low_level_zmod_adc_dac I next decided to run the zmod_dac demo using both petalinux and baremetal. https://github.com/Digilent/Eclypse-Z7/tree/zmod_dac/master I was able to program the FPGA and also run the code, however every time it attempts to allocate a buffer to transfer the waveform via AXI DMA malloc is returning a 0/NULL value for the buffer address. If I am correct this means that mal
  3. Hello! I'm working on tutorial how to port and use PYNQ with Eclypse-Z7 and now I'm stuck on ZMOD integration. I have created device-tree-overlay based on PL.dtsi generated by petalinux with PYNQ-PRIO, applied some changes by hand and I don't know why I'm getting this error. Everything is here: https://www.hackster.io/bartosz-rycko/eclypse-z7-pynq-porting-guide-3dd24c If you could help me on this I would be grateful. Thanks :)
  4. No, not those kinds of phasers... I'm talking about the much more fun mathematical concept of phasors! But if you have an Eclypse-Z7, and want to tag along, then you might get a little stunned anyway, so try it out for yourself. EclypseZ7_PhasorToy_release_R042.zip
  5. zygot

    EclypseZ7 curiosity

    I've recently been experimenting on the Eclypse-Z7 and have run into a curious problem. I created a board design with BRAMs having one port external for HDL access. I've run into a problem where the program hangs if I try to access the BRAM using a pointer rather than the driver. I thought that this was my coding error until I create a new application in the SDK using the predefined memory test. This compiled automatically and also hanged trying to access the bram. When I pressed btn0 on the board, the standard memory test application went on to complete testing both brams properly. btn0