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Showing results for tags 'drive strength'.
Hello. Reading the Manual I saw the following. 5. Digital I/O Figure 22 shows half of the Digital I/O pin circuitry (the other half is symmetrical). J3 is the Analog Discovery 2 user signal connector.General purpose FPGA I/O pins are used for Analog Discovery 2 Digital I/O. FPGA pins are set to SLOW slew rate and 4mA drive strength, with no internal pull. PTC thermistors provide thermal protection in case of shortcuts. Schottky Diodes double the internal FPGA ESD protection diodes for increasing the acceptable current in case of overvoltage. Nominal resistance of the PTCs (220Ω
I am using an ARTY board. I have just used the constraints as is without making any changes. I do not see any constraints for drive strength or Slew rate attribute anywhere in the XDC file. I am wondering how it is determined that the default values are sufficient for these attributes. For example for the Ethernet PHY i browsed thru the datasheet but didnt see anything that would make it clear to select 12mA (default) drive strength for those pins.