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Found 16 results

  1. Hello, I am new to Zybo/FPGA and currently going thru the tutorial that's available. Currently at the DMA tutorial. From what I understand, there are 2 method to do the project, using SDK or Vivado. When I tried using SDK, I have a whole bunch of missing inlcudes like xparameters.h, xgpio.h, xstatus.h (to name a few). So, I went the Vivado route. When attempting to run the tcl script, I had errors on line 67. update_ip_catalog -rebuild. Was able to resolve that by using the vivado library. Now, I'm stuck with errors stating that IPs are locked. I am trying to follow this recommendation to change the version, but, I can't find the system.tcl file. Any suggestions?
  2. Hi I am trying to run the fsbl and hello world on Zybo-z7-10, but seems like it does not work. When I tried to run the fsbl, it shows the message like this. I build this project step by step learning from a video on youtube, the hardware and software part. I post this link at the bottom. The output in terminal is supposed like this, tell me Boot mode is JTAG, but now it is not. Does anyone know why this happen? If FSBL does not run successfully, the other parts in my project won't work as well since the the clock and interrupts from PS side are not activated. For example, in EnableSampleGenerator, I assign 32 and 1 to GPIO, but when I read from it, they are still 0. Also after I start first DMA transmission, when it finishes, there should be an interrupt, and in the interrupt I start another DMA transmission. Now seems like the interrupt never happens, so I seriously doubt the FSBL does not run properly. Thanks a lot in int main()
  3. lukap

    I2S IP core and AXI DMA

    Hello. I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github. I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I understand how the DMA works. I'm basing my code on the Xilinx' interrupt DMA example, so I think the initializations and similar are done correctly. What I'm unsure of is the following: I start the S2MM (Stream to Memory Mapped - I2S to RAM) transfer with the number of bytes to be transferred and expect the I2S controller to only output data when it has it (similarly as in the Zybo base system example, except that there the fifo status register is checked, but for the streaming interface I expect this to be taken care of in the IP). So if I want to transfer 5 seconds of audio, I start the transfer of 5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample For now I then wait for the interrupt in which a flag is set, so that I know the transfer has finished. I expect this to last 5 seconds but instead it happens in a couple hundred ms (I don't have an o-scope) and only a few samples arrive. So is my understanding correct? Has anyone ever tried interfacing the I2S core to an AXI DMA?
  4. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  5. Hi all, actual i try to transfer a data stream from the DMA via uart to my PC. In my design an DDS-compiler generates a 32bit sine wave, which should be transfered via uart and read by a python script. The general data transfer works, but sometimes i get some noisy signal. This signal happens also when using a lower sample rate. For the uart data transfer actual i did not add any marker where the 32 bit value begins or ends. So i expect this is the problem, but i don't know how to include this in my SDK and python code. Maybe any suggestion? (The FPGA design is similar to my previous post https://forum.digilentinc.com/topic/8966-axi-dma-timing/?page=0#comment-26920 using the Cmod A7) Plot of the result with pyqtgraph: SDK code: int XAxiDma_Poll_Uart(u16 DeviceId) { int Status, Index; int Tries = NUMBER_OF_TRANSFERS; u32 *RxBufferPtr; u32 *RxPacket; u8 BytesSent; RxBufferPtr = (u32 *) RX_BUFFER_BASE; RxPacket = (u32 *) RX_BUFFER_BASE; for (Index = 0; Index < MAX_PKT_LEN_WORDS; Index ++) { RxBufferPtr[Index] = 0xCC; } /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled*/ Xil_DCacheFlushRange((u32)RxBufferPtr, MAX_PKT_LEN); Status = XAxiDma_SimpleTransfer(&AxiDma, (u32) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) {return XST_FAILURE;} while (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) {/* Wait*/} /* Invalidate the TestBuffer before receiving the data, in case the Data Cache is enabled*/ Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN); //send data to uart BytesSent = XUartLite_Send(&UartLite, RX_BUFFER_BASE, sizeof(RxPacket)); while (XUartLite_IsSending(&UartLite)) {/*Wait*/} return XST_SUCCESS; } Python code: import numpy as np import sys import serial buffersize = 512 byte_number = 4 ser = serial.Serial( port='COM6',\ baudrate=921600,\ parity=serial.PARITY_NONE,\ stopbits=serial.STOPBITS_ONE,\ bytesize=serial.EIGHTBITS,\ timeout=0) for u in range(20): #read serial buffer s = ser.read(buffersize) #convert to integer for i in range (int(len(s)/byte_number)): res_value = dataSerial[(i*byte_number):((i+1)*byte_number)] value = int.from_bytes(res_value, byteorder='little', signed = True) dataSerialFormated = np.append(dataSerialFormated, value)
  6. Weevil

    Axi DMA timing

    Hi all, i am using the DMA to send data from my DDS-compiler to DDR on the Arty board. The data transfer works in general, but actual the timing is wrong. My actual Design: I generate a 2 Hz clock and transfer with 2 Hz values from the DDS to the DMA. The problem is, if i start the simple_poll-function from this code/design (http://i.imgur.com/7v0d7NF.png) it takes the same value many times. So finally the aim is to get a value every time the DDS provides a new one. Thanks to everyone who can help!
  7. Weevil

    Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  8. Nystflame

    AXI DMA and Microblaze

    Hello All, I seem to be having an issue that I cannot quite track down the cause of... My overall goal is that I would like to write ADC samples into DDR memory via a DMA. I am able to DMA samples into the DDR successfully, except that the first couple values in DDR are incorrect. I've noticed that if I aquire some samples, and read the DDR, the first 4 are old samples which seem to update the next time I do an acquisition of ADC samples. I've also noticed that after the first DMA transfer, if I read the s2mm_length register, it seems to be a few transfers short of what I programmed the transfer length to be. But if I do another transfer, and all subsequent transfers from then on, they seem to be equal to the length which was programmed. I initially thought that this was a caching issue (and still may be), but I've since disabled caching in the software. I've also provided an image below of my Microblaze, and to my understanding there is no caching enabled (i've disabled cache when configuring the Microblaze in vivado). The type of DMA transfer that I am using is just a register direct transfer, not scatter gather. The M_AXI_DP is connected to an AXI Interconnect, of which the M_AXI port of the interconnect is connected to the S_AXI_LITE port of the DMA. Another interesting thing I've noticed is that, if I do an acquisition of ADC samples, read the DDR starting at address 0, and perform another read of DDR starting at address 0, it looks like the data at address 0 updates, but the following data is the same as the first read. P.S. I am still new to Digital Design, sorry if I've omitted any crucial information.
  9. hello, I used the zybo_hdmi_in as reference for my project. I struggled with the VDMA. After some modifications (added image sensor as input) It seems so I have my program code overlapping with the DDR memory of my frame buffer. I found that my design works once I added an offset to the DDR_0_BASEADDRess. Without the offset the VDMA gives an address encoding error. I increased the offset until it works. Now, the printf's are no longer showing... Looking into UG585 (TRM) the VDMA is definetely within the address range 0010_0000 to 3FFF_FFFF and there seem no overlap. Can anyone suggest me a good document where I can learn more about Zynq memory mapping, and observe problems like stack overflow etc? thanks
  10. Hi, I want to run simple DMA transfer (not using scatter gather) application program on the attached design. But the program is always hung when running XAxiDma_CfgInitialize(&AxiDma, Config) function. The JP4 jumper is set on QSPI mode and the running configuration mode is like the figure I attached. The same program is run and not hung on XAxiDma_CfgInitialize(&AxiDma, Config) if ran on ZYBO. But, with differences in run configuration mode. On ZYBO run configuration mode, I'm not using the initialization file and so not run the ps7_init. On Arty Z7 I need to use it, because if I'm not using it the internal error (No target with ID 64 in the system) will be occured. What should I do?
  11. I am doing a project with some audio DSP. For this I am using the audio codec on the Zybo. The first thing I want to do, is to be able to record and playback audio with a little delay between input and output. In order to speed up the development process, I decided to use the DMA Audio demo. But I'm lacking some information or rather some documentation. So is there any of your guys who knows which registers is references to here (Audio controller registers) in the code below. Since I2S is an hardware interface standard, so there should not be any registers. So I think it has something to do with DMA. But I can't find any documentation, which fits. Do anybody know which documentation would give a insight to the registers? #define AUDIO_CTL_ADDR XPAR_D_AXI_I2S_AUDIO_0_AXI_L_BASEADDR //Audio controller registers enum i2sRegisters { I2S_RESET_REG = AUDIO_CTL_ADDR, I2S_TRANSFER_CONTROL_REG = AUDIO_CTL_ADDR + 0x04, I2S_FIFO_CONTROL_REG = AUDIO_CTL_ADDR + 0x08, I2S_DATA_IN_REG = AUDIO_CTL_ADDR + 0x0c, I2S_DATA_OUT_REG = AUDIO_CTL_ADDR + 0x10, I2S_STATUS_REG = AUDIO_CTL_ADDR + 0x14, I2S_CLOCK_CONTROL_REG = AUDIO_CTL_ADDR + 0x18, I2S_PERIOD_COUNT_REG = AUDIO_CTL_ADDR + 0x1C, I2S_STREAM_CONTROL_REG = AUDIO_CTL_ADDR + 0x20 };
  12. Hi, I recently purchased a Zybo board and used the DMA Audio Demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start) to acquire audio input and output. The Audio codec records 5 seconds of audio and then passes it to the Zynq PL via I²S protocol, that is it transmits the bit clock BCLK, the word select RECLRC and the data recorded RECDAT. My goal is to take this data and apply a filter on it, before the stream is mapped into memory with a DMA and then sent back to the audio codec and played in earphones. But I don't really understand how the data is received by the PL and where to find it (in some buffer I guess) in order to take it, process it, and then put it back in a different buffer where the DMA could access it and do his thing. Does anyone have experience with this demo that could help me figure this out ? Thanks, Lucile
  13. Hi everyone, I'm trying to use the axi_dma xilinx driver in order to make transfer between PS and PL in both way. I posted this issue on the xilinx forum but I didn't get any response. This is the link: https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-DMA-test-err... Now I'm using the version 2016.3 for both software, Vivado and Peralinux. Any idea?? I have looked for across the web but I cannot be able to manage the axidma engine. Thanks in advance Best,
  14. akashvakil

    zybo audio

    Hi, I was trying to get started with ZYBO audio. I have followed steps as seen in tutorial. I am using Vivado 2016.2 as prescribed. But when I run the TCLfiles I have the following errors.: ERROR: [IP_Flow 19-3461] Value 'hdmi_in_ddc' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell 'axi_iic_0' . Valid values are - Custom INFO: [IP_Flow 19-3438] Customization errors found on 'axi_iic_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors. How does one fix this? tia
  15. zoggx003

    Zybo DMA example

    I downloaded the ZYBO-master from the github, and ran the tcl script from the following directory: C:\Zynq_Book\ZYBO-master\ZYBO-master\Projects\dma\proj. Could the tcl files have been mixed up or misplaced? Has anyone fIgured out how to fix this? this is the error that I get: ERROR: [IP_Flow 19-3461] Value 'hdmi_in_ddc' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell 'axi_iic_0' . Valid values are - Custom INFO: [IP_Flow 19-3438] Customization errors found on 'axi_iic_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors. while executing "rdi::add_properties -dict {CONFIG.IIC_BOARD_INTERFACE hdmi_in_ddc CONFIG.USE_BOARD_FLOW true} /axi_iic_0" invoked from within "set_property -dict [ list CONFIG.IIC_BOARD_INTERFACE {hdmi_in_ddc} CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_0" (procedure "create_root_design" line 55) invoked from within "create_root_design """ (file "../src/bd/system.tcl" line 1498) while executing "source $origin_dir/src/bd/system.tcl" (file "./create_project.tcl" line 102) update_compile_order -fileset sources_1
  16. Hi. I managged to run both Linaro and ArchLinux on the Zybo board, with HDMI output (but i'm gonna remove it after). But I'm having some troubles to comunicate with my custom hardware. I'm used to programming in Hardware, and I made several real time high performance applications like face recognition and real time video processing on pure verilog (Nexys 3, Nexys 4, Atlys boards), but I'm kind of new to cross-compiling, linux kernels, and drivers. I have a few master AXI modules that directly communicates with the DDR3 memory using the HP ports (no DMA, VDMA or similiars), and I just reserve a fraction of the DDR3 memory to work with them. Now in Linux, all the address are virtual, so I must write a driver, or find a way to allocate physicall contiguous memory in software. -My IP usually work this way (e.g this is a sobel filter): It receives the base address where the image to process is located (usually is XRGB888 format), the resolution of the image, several arguments like threshold, and it outputs directly the result on the VGA port or HDMI port or a touchscreen that I have (all of them are custom IP) or it write the output on the DDR3 memory. If the flow requires SW interventions, It triggers a interrupt. Now that I'm using Linux, I have 3 options: Use DMA: I kind of know how to use DMA on baremetal on the software side, but I have no idea how to make a custom IP that comunicates with the DMA modules. I have a decent understanding how master and slave AXI full interfaces works tough.Write a custom driver that works the way my IP needs.Hack with things like dma-mapping, contiguous memory allocations, memory maps, etc.Make a "don't touch" region of ram for Linux, so the HW can work with it.With simple AXI peripherals that are mapped to a fixed address (0x4XXXXXXX) and doesnt communicate with the DDR3, I use mmap and to access the registers, and it work well, but I can't use interrupts. With peripherals that use the DDR3, the configuration parts is done the same way that the regular AXI peripherals, but the RAM buffer, needs to be reserved so Linux doesn't write to it, or it only do it on my command. Also I need the physicall address of that reserverd ram region to pass it to the peripheral. I'd like some highlights on how to make a custom DMA module (hardware side please), but any of the 4 options works. PS: Also, some of these modules that work with RAM doesn't even have an slave axi interface, so they won't appear on the automatic generated device tree. Any information would be usefull. Best regards. Alejandro Wolf.