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Found 28 results

  1. Digilent Xilinx Research Labs XUP Virtex-II Pro Development System Board On Ebay https://www.ebay.com/itm/Digilent-Xilinx-Research-Labs-XUP-Virtex-II-Pro-Development-System-Board/181537140568?
  2. Hello, I ordered a brand new Analog Discovery bundle directly from Digilent a few weeks ago for use in a college class, but every time I have attempted to build a simple circuit and connect the board to WaveForms, I consistently get one of the two attached errors. The components of the parts kit have been working fine but it seems like there is a problem with the amount of power being supplied to the Analog Discovery board itself. Any help would be greatly appreciated. Thanks, bucklc2
  3. ATIF JAVED

    Hardware manager recognize problem

    Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  4. Digilent Atlys Spartan 6 Xilinx FPGA Board 410-178 On Ebay https://www.ebay.com/itm/Digilent-Atlys-Spartan-6-Xilinx-FPGA-Board-410-178-Board-ONLY/253868531684?
  5. vinay_shenoy

    SD Mode Operation for PmodSD

    Hello, Does PmodSD (https://reference.digilentinc.com/reference/pmod/pmodsd/reference-manual) support SD mode of operation? Is it designed only to work with SPI mode as written in the reference manual? Please let me know Regards, Vinay Shenoy
  6. Hi evryone ! I can't understand my problem, I have nothing on the console SDK. Knowing that I have the right driver and i successfully program FPGA and I'm on the right port. I am using Vivado 2016.2 ubunto linux and Zybo-z7-10 as board in vivado I create another project and I clean but the problem still persists ! plzz help ! I want just display a hello world with a simple a bitstream (Axi lite generated by vivado).
  7. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board. The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design). However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design). Can anyone help me figure out why this is happening? Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board: SOURCES: ---------------- -- pindelivery.vhd -- Routes package pins to logical units library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity pindelivery is Port ( clk_in : in STD_LOGIC; rst_in : in STD_LOGIC; leds_out : out STD_LOGIC_VECTOR (3 downto 0)); end pindelivery; architecture behavioral of pindelivery is component topLevel_debug port (clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector(3 downto 0)); end component; signal rst_out : std_logic := '0'; begin rst_out <= not rst_in; tld1 : topLevel_debug port map (clk => clk_in, rst => rst_out, led_out => leds_out); end behavioral; ---------------- -- topLevel_debug.vhd -- Top-level module for debug library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity topLevel_debug is port ( clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector (3 downto 0)); end topLevel_debug; architecture behavioral of topLevel_debug is component controlTest port (clk : in std_logic; rst : in std_logic; r0_highnibble : out std_logic_vector(3 downto 0)); end component; begin cpu1 : controlTest port map (clk => clk, rst => rst, r0_highnibble => led_out); end behavioral; ---------------- CONSTRAINTS: ---------------- ## Clock signal set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }]; ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Reset button set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property INTERNAL_VREF 0.675 [get_iobanks 34] ---------------- Any assistance would be much appreciated! Thanks, Curt Pehrson
  8. M.Saad Ikram

    XAPP 495 fixed on digilent atlys spartan 6

    Hi, I was trying to get a single input from J3 to show on HDMI out J2 using xapp495 fixed on which can be downloaded as: https://joelw.id.au/FPGA/DigilentAtlysResources The problem that I am getting is that my output monitor says that it is NOT OPTIMUM MODE. RECOMMENDED MODE IS 1920x1080. The configuration of the jumper wires is shown in the figure below. I tried all button configurations but didnt see a single frame. I tried to implement VTC_DEMO seperately and I was able to see some coloured pattern generated on the monitor but if I implement DVI_demo/...... It took a lot out of me but didnt give me anything....... Serious help required from the professional engineers out there. thank you
  9. I recently purchased the chipkit UC32 from digilent to do a labview project but when I connect it to my Windows 10 laptop, it says “USB device not recognized”. In the device manager of my computer I see the error in the port under Universal Serial Bus Controllers and it has the yellow triangle error symbol next to “Unknown USB Device (Device Descriptor Request Failed)” I have tried many things to try and get it working but have failed. Please help
  10. Raphael Christian

    CMOD A7 System Generator

    Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  11. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  12. Jerome

    VHDCI cable datasheet

    Hello, Can you please share a datasheet of the VHDCI cable sold on your store : http://store.digilentinc.com/vhdci-male-to-male-cable/ I am particularly interested by the internal wiring of the cable, which pairs are twisted together, etc... Thanks Jerome
  13. Hi everyone, I downloaded digilent.waveforms_3.2.6_armhf.deb and installed it on my system. The "dwfcmd" command is working fine and the python examples also work. Now I want to compile the C examples and I keep getting errors: analogin_trigger.c:(.text+0x74): undefined reference to `FDwfDeviceOpen' analogin_trigger.c:(.text+0x9c): undefined reference to `FDwfGetLastErrorMsg' analogin_trigger.c:(.text+0xd4): undefined reference to `FDwfAnalogInFrequencySet' analogin_trigger.c:(.text+0xec): undefined reference to `FDwfAnalogInBufferSizeSet' analogin_trigger.c:(.text+0x110): undefined reference to `FDwfAnalogInChannelEnableSet' analogin_trigger.c:(.text+0x128): undefined reference to `FDwfAnalogInChannelRangeSet' analogin_trigger.c:(.text+0x13c): undefined reference to `FDwfAnalogInTriggerAutoTimeoutSet' analogin_trigger.c:(.text+0x154): undefined reference to `FDwfAnalogInTriggerSourceSet' analogin_trigger.c:(.text+0x168): undefined reference to `FDwfAnalogInTriggerTypeSet' analogin_trigger.c:(.text+0x17c): undefined reference to `FDwfAnalogInTriggerChannelSet' analogin_trigger.c:(.text+0x190): undefined reference to `FDwfAnalogInTriggerLevelSet' analogin_trigger.c:(.text+0x1a4): undefined reference to `FDwfAnalogInTriggerConditionSet' analogin_trigger.c:(.text+0x1f4): undefined reference to `FDwfAnalogInConfigure' analogin_trigger.c:(.text+0x208): undefined reference to `FDwfAnalogInStatus' analogin_trigger.c:(.text+0x248): undefined reference to `FDwfAnalogInStatusData' analogin_trigger.c:(.text+0x2dc): undefined reference to `FDwfDeviceCloseAll' I used clang and gcc to build the analogin_trigger.c sample: clang analogin_trigger.c Where is my mistake?
  14. WTB!!! in need of any / all Working Digilent Xilinx Virtex 5 FPGA boards for a company project! paying "cash" via paypal!!! pls PM me if you have a Genesys Virtex 5 board in 100% working order that you want to ditch, upgrade, or need cash. Thanks! -H
  15. I am attempting to sample values from the XADC and use those values to control a video display connected via VGA. Both of these parts work separately, but when I attempt to combine the hardware for the two, the XADC stops working. Specifically, the XADC still returns values, and those values still fluctuate slightly, but they don't represent the voltage anymore. I'm using the XADC in single channel mode, and have tried both channels 6 and 14. I've connected my analog input to PMOD-JA in the appropriate places for channel 6 and 14. Both of these channels function perfectly in my XADC only design, but when I add the VGA display hardware they stop working. The values returned by the XADC still fluctuate, so it's sampling something, just not the thing I want it to sample. For example, I had a voltage difference of approximately 0.37 volts across channel 14 and some of the 16-bit values returned by the XADC were 206, 187, 196, 226, 201, 220, 201, 187, 222, 229, 192, 213, and 225. These values stay in this 100-200 range even if the voltage is changed. Again, the correct values are returned when using the hardware without the VGA display. Adding the VGA hardware breaks it. I'm interested to know if anyone has successfully used both the VGA output and the XADC in the same project, and if they had to do anything special to get the setup working. If necessary, I could provide code or a Vivado project that demonstrates my issue. Thanks!
  16. Hi all, I am currently doing the Xilinx tutorial to run Linux on my zybo : http://www.wiki.xilinx.com/Build+FSBL In the process, I have to get these task done : Bitstream (for the programmable logic portion) System hardware project hdf file My question is : can I use the https://reference.digilentinc.com/_media/zybo/zybo_base_system.zip ...to generate the bitstream and the system hardware project ? If I complete the tutorial with the generated files, will I be able to run linux and use it with the hdmi or vga output, get access to any kind of command prompt? Thanks. Regards, Herrmattoon
  17. If you hear of or author a textbook featuring a Digilent product, we want to know about it! So far, we have the following list compiled: Digital Design Using Digilent FPGA Boards Verilog/Active -HDL Edition by Haskell & Hanna Introduction to Digital Design Using Digilent FPGA Boards- VHDL Edition by Haskell & Hanna PIC32 Microcontrollers and the Digilent chipKIT: Introductory to Advanced Projects by Ibrahim Real Digital: A Hands-on Approach to Digital Design by Cole FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version by Chu Getting Started with chipKIT: The Arduino Compatible PIC32 Based Module by Hellebuyck Synthesis and Optimization of FPGA-Based Systems by Sklyarov & Skliarova iLab Analog by Chen Yun Chao Digital Fundamentals by Floyd The Zynq Book by Crockett, Elliot, Enderwitz, Stewart Beginning C for Arduino by Purdum Electrical Engineering Practicum by Bowman FPGA Based System Design by Memon, Hassan & Memon Introduction to Electric Circuits 9th edition, by Jackson/Temple/Kelly
  18. Hi every one. I was Created HLS Ip Core. This Core is a simple Image Filer, and the input for this Core is a matrix of picture that I built in Matlab, Now I'm trying to have a input from HDMI and filter output from VGA. In other words, I don't know "How create a simple block design in ZYBO for have HDMI input, VGA output and HLS IP CORE?" and "Which commands need to read frames from input in SDK sowftware?" Best regards. Abish SJ
  19. Digilent Waveforms depends on xdg-utils which depends on x11 and many things. Can I install waveforms without all of this and how? Is anyone using this on an embedded device like the Beaglebone Black or Rasberry Pi?
  20. ManuelPA

    Arty DDR3, max frequency

    I´m learning the arty board, so i just want to know which is the max frequency for write/program on the DDR3, using vivado and microblaze
  21. Hello all This is related to the current hardware: Chipkit Max32 with Network Shield. Issue: Xively library files will not work with chipkit max32+ethernet shield. I have been suffering this change for a while, the MPIDE 2015 release got botched with the arduino update. I had to download the 2015 test release or rely on the totally functional 2013 release. Currently using the MPIDE 2015 test release. So, later on, getting the Xively library files proved to be difficult to utilize, errors on top of errors. Other option was to use the chipkit-core library files also available for Arduino IDE. But the network shield fails to operate. Xively library files worked without any errors. Now, I can either work with xively library files on Arduino IDE or operate the network shield through the MPIDE. Has anyone figure out if there is a solution for any of my issues? Debugging the code is insane after the update.
  22. Hi I have bought a NEXYS 4 cell memory version. I have downloaded Vivado webpack. I see Diligent offers some software for instrument tools, such as NI Multisim & NI Ultiboard (NI Circuit Design Suite) it says $40 but it says academic. Can non students purchase this software? Will any of the software listed on this page help me? I am wondering now if i should of bought the Baysys 3 as i found out that the Vivado a locked in version comes bundled with it. What does a locked version entail? I am very much a novice in this venture. I need any kind of tool that is a available for the process. Unfortunately, I can't get any funding till i can prove the concept. This means i can't afford buying high dollar software. I know Xilinix got rid of the Statecad and Simulator in ISE 11, in what version of ISE did they eliminate schematics or did they? The only reason I want ISE is Schematic capability and ISE 10 can't work on a Win 7 machine. I have an XP one also so I can use 10 there. Thanks Rex