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Found 36 results

  1. Digilent Xilinx Spartan 3 Starter Board Includes JTAG3 w/SPI To Parallel Cable On Ebay
  2. XILINX Digilent Basys 2 Board - Spartan3E-250 FPGA Development Kit On Ebay
  3. Digilent Xilinx XUP Virtex-II Pro Development System On Ebay
  4. Dear Diligent AD2 team Please can you update your companies notes supporting Microsoft .net drivers which work with C# and and F# for the Analog Discovery 2 tool. It is a an excellent tool , but be even more excellent if could work and be used in the microsoft .net environment. This is a link to a previous forum post on the subject which used visual basic 6 from a while back. The original visual basic 6 example . From the time before .net happened >> I have taken this worked example and updated to get it to run with in visual studio 2017 .See enclosed attachment- It is failing to work properly due a. dll memory project fault in the .dll driver. The C++ source code for the .dll driver is also included in the attachment. My request is can Digilent fix the driver so that is usable in .net assemblies and is Memory safe . This is the reported run time fault when trying to access FDwfDeviceOpen in line of code : nRet = FDwfDeviceOpen(-1, hdwf) Fault report : System.AccessViolationException HResult=0x80004003 Message=Attempted to read or write protected memory. This is often an indication that other memory is corrupt. Source=<Cannot evaluate the exception source> StackTrace: <Cannot evaluate the exception stack trace> Thank you for considering this request
  5. I plan on purchasing the Zybo z7-20 for prototyping a project I am working on. After looking at the documentation for the board it says that Vivado WebPack supports the Zybo z7 board and is fully compatible with Design Suite. I just want to make sure that Xilinx Vivado WebPack works with this board. Thanks
  6. Digilent Electronics Explorer Board On Ebay
  7. Digilent chipKIT Network Shield - 2x CAN, Ethernet, 2x I2C, USB On Ebay
  8. Digilent Xilinx Research Labs XUP Virtex-II Pro Development System Board On Ebay
  9. Digilent Xilinx Research Labs XUP Virtex-II Pro Development System Board On Ebay
  10. Hello, I ordered a brand new Analog Discovery bundle directly from Digilent a few weeks ago for use in a college class, but every time I have attempted to build a simple circuit and connect the board to WaveForms, I consistently get one of the two attached errors. The components of the parts kit have been working fine but it seems like there is a problem with the amount of power being supplied to the Analog Discovery board itself. Any help would be greatly appreciated. Thanks, bucklc2
  11. Hello All of you I am trying to debug my code on picozed board . Board is successfully recognized in my college desktop PC but when i tried to connect it in my pc(vivado 2017.4 window 10) hardware manager . It give me error that no hardware is open . I use diligent JTAG-USB programming cable for debugging . I recheck drivers and found out that cable is also identified by PC. Please give me a suggestion what should i do. Below you can find the screenshots of device manager for driver installation and hardware manager status.
  12. Digilent Atlys Spartan 6 Xilinx FPGA Board 410-178 On Ebay
  13. Hello, Does PmodSD ( support SD mode of operation? Is it designed only to work with SPI mode as written in the reference manual? Please let me know Regards, Vinay Shenoy
  14. Hi evryone ! I can't understand my problem, I have nothing on the console SDK. Knowing that I have the right driver and i successfully program FPGA and I'm on the right port. I am using Vivado 2016.2 ubunto linux and Zybo-z7-10 as board in vivado I create another project and I clean but the problem still persists ! plzz help ! I want just display a hello world with a simple a bitstream (Axi lite generated by vivado).
  15. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to 4 LEDs on the board. The purpose is to monitor the high nibble of a 32-bit ALU calculation using the LEDs on the Arty board. The design works under behavioral simulation, and it elaborates correctly (see attached schematic of the elaborated design). However, when I synthesize the design, it is reduced to almost nothing -- with the clock and reset pins routed nowhere, and the LED pins routed to some buffers connected to ground. The entire internals of the design are removed (see included schematic of the synthesized design). Can anyone help me figure out why this is happening? Here are the sources of the upper levels of the design, and the relevant constraints that I've applied for the FPGA board: SOURCES: ---------------- -- pindelivery.vhd -- Routes package pins to logical units library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity pindelivery is Port ( clk_in : in STD_LOGIC; rst_in : in STD_LOGIC; leds_out : out STD_LOGIC_VECTOR (3 downto 0)); end pindelivery; architecture behavioral of pindelivery is component topLevel_debug port (clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector(3 downto 0)); end component; signal rst_out : std_logic := '0'; begin rst_out <= not rst_in; tld1 : topLevel_debug port map (clk => clk_in, rst => rst_out, led_out => leds_out); end behavioral; ---------------- -- topLevel_debug.vhd -- Top-level module for debug library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.cpu1_globals_1.all; entity topLevel_debug is port ( clk : in std_logic; rst : in std_logic; led_out : out std_logic_vector (3 downto 0)); end topLevel_debug; architecture behavioral of topLevel_debug is component controlTest port (clk : in std_logic; rst : in std_logic; r0_highnibble : out std_logic_vector(3 downto 0)); end component; begin cpu1 : controlTest port map (clk => clk, rst => rst, r0_highnibble => led_out); end behavioral; ---------------- CONSTRAINTS: ---------------- ## Clock signal set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { clk_in }]; #IO_L13P_T2_MRCC_15 Sch=uclk create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { clk_in }]; ## LEDs set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { leds_out[0] }]; #IO_L16N_T2_A27_15 Sch=led[2] set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[1] }]; #IO_L17P_T2_A26_15 Sch=led[3] set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { leds_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { leds_out[3] }]; #IO_L18P_T2_A24_15 Sch=led[5] ## Reset button set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { rst_in }]; #IO_L11N_T1_SRCC_15 ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property INTERNAL_VREF 0.675 [get_iobanks 34] ---------------- Any assistance would be much appreciated! Thanks, Curt Pehrson
  16. Hi, I was trying to get a single input from J3 to show on HDMI out J2 using xapp495 fixed on which can be downloaded as: The problem that I am getting is that my output monitor says that it is NOT OPTIMUM MODE. RECOMMENDED MODE IS 1920x1080. The configuration of the jumper wires is shown in the figure below. I tried all button configurations but didnt see a single frame. I tried to implement VTC_DEMO seperately and I was able to see some coloured pattern generated on the monitor but if I implement DVI_demo/...... It took a lot out of me but didnt give me anything....... Serious help required from the professional engineers out there. thank you
  17. I recently purchased the chipkit UC32 from digilent to do a labview project but when I connect it to my Windows 10 laptop, it says “USB device not recognized”. In the device manager of my computer I see the error in the port under Universal Serial Bus Controllers and it has the yellow triangle error symbol next to “Unknown USB Device (Device Descriptor Request Failed)” I have tried many things to try and get it working but have failed. Please help
  18. Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  19. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  20. Jerome

    VHDCI cable datasheet

    Hello, Can you please share a datasheet of the VHDCI cable sold on your store : I am particularly interested by the internal wiring of the cable, which pairs are twisted together, etc... Thanks Jerome
  21. Hi everyone, I downloaded digilent.waveforms_3.2.6_armhf.deb and installed it on my system. The "dwfcmd" command is working fine and the python examples also work. Now I want to compile the C examples and I keep getting errors: analogin_trigger.c:(.text+0x74): undefined reference to `FDwfDeviceOpen' analogin_trigger.c:(.text+0x9c): undefined reference to `FDwfGetLastErrorMsg' analogin_trigger.c:(.text+0xd4): undefined reference to `FDwfAnalogInFrequencySet' analogin_trigger.c:(.text+0xec): undefined reference to `FDwfAnalogInBufferSizeSet' analogin_trigger.c:(.text+0x110): undefined reference to `FDwfAnalogInChannelEnableSet' analogin_trigger.c:(.text+0x128): undefined reference to `FDwfAnalogInChannelRangeSet' analogin_trigger.c:(.text+0x13c): undefined reference to `FDwfAnalogInTriggerAutoTimeoutSet' analogin_trigger.c:(.text+0x154): undefined reference to `FDwfAnalogInTriggerSourceSet' analogin_trigger.c:(.text+0x168): undefined reference to `FDwfAnalogInTriggerTypeSet' analogin_trigger.c:(.text+0x17c): undefined reference to `FDwfAnalogInTriggerChannelSet' analogin_trigger.c:(.text+0x190): undefined reference to `FDwfAnalogInTriggerLevelSet' analogin_trigger.c:(.text+0x1a4): undefined reference to `FDwfAnalogInTriggerConditionSet' analogin_trigger.c:(.text+0x1f4): undefined reference to `FDwfAnalogInConfigure' analogin_trigger.c:(.text+0x208): undefined reference to `FDwfAnalogInStatus' analogin_trigger.c:(.text+0x248): undefined reference to `FDwfAnalogInStatusData' analogin_trigger.c:(.text+0x2dc): undefined reference to `FDwfDeviceCloseAll' I used clang and gcc to build the analogin_trigger.c sample: clang analogin_trigger.c Where is my mistake?
  22. WTB!!! in need of any / all Working Digilent Xilinx Virtex 5 FPGA boards for a company project! paying "cash" via paypal!!! pls PM me if you have a Genesys Virtex 5 board in 100% working order that you want to ditch, upgrade, or need cash. Thanks! -H