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Found 6 results

  1. PTSmith

    CMOD A7 100 MHz clock in

    So, I want to bring in a 100 MHz clock and route it to a CMT to generate a bunch of lower frequency clocks all phase-locked to the 100 MHz. I appreciate I can't output an LVDS signal, but it looks like I should be able to bring in an LVDS signal as long as I supply my own 100 ohm termination to pins 18 and 19 for example. Am I missing anything? Paul Smith Indiana University Physics
  2. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) 2nd trial : clk_front & back : LVCmos25 and clk_40_P & N : LVDS25 -> result : LVCmos25 ,(bank35) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) thank you for your help!
  3. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
  4. Hi, I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below. set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board. Thank you
  5. How do I implement an external differential clock in VHDL for the CMOD S7? Vivado keeps on telling me to inset this flag in my constraint file: set_property CLOCK_DEDICATED_ROUTE FALSE However, I care about timing because it's an external clock signal. I'm using a clock dedicated route(Pmod pin are 2×6) as seen in this schematic.
  6. Hi Folks Although the Analog Discovery has fully differential analog (scope) inputs, the Discovery BNC adapter board does NOT! For some reason the negative inputs of both analog channels have been connected to the Analog Discovery ground. Therefore, they form a short circuit between any conductors they are connected to. Why is this important? I just found out the hard way, when I connected the scope leads from the Discovery BNC adapter board to parts of a circuit at very different voltages. I was expecting each channel to measure the differential voltage across each probe. Instead, there was a crack, a flash, and a little jet of molten metal, as the clip on one of my scope probes vaporised! IMO this is a safety hazard, because adding the Discovery BNC adapter board to the Analog Discovery changes its electrical behaviour in a significant way (from differential to single ended) but there is no mention of this in the Discovery BNC adapter board reference manual. Users should be warned in BIG LETTERS about this change in behaviour, perhaps printed on the PCB as well. I was lucky, but providing users with a warning about this could save somebody's life one day. I can see that grounding the negative inputs could make sense, in that it makes the analog inputs behave more like a conventional oscilloscope, where the probe shields are usually returned to Earth. However, if you're going to do this you should at least warn users about what you've done. IMO it would be better to provide 4 sockets for scope probes, with each connected to one of the differential inputs, and all the scope shields returned to Analog Discovery ground. Then the Discovery BNC adapter board could be used for fully differential measurements. You could also provide jumpers to select single ended behaviour instead, by shorting the negative inputs to ground. At least that would give the user a choice about whether to operate as differential or single ended inputs.