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Found 4 results

  1. Hello, I'm designing a custom FMC board to use with my Genesys 2. Is there any informations about GTX and serdes pair length ? Thanks
  2. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS mandate 2.5V rail voltage in 7Series devices. Is it possible to alter the feedback resistor network for FB1 (shown on pg. 10 of https://reference.digilentinc.com/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_b.pdf) to convert Vcco 3.3V to 2.5V? I believe by reducing R200 from 31.6K to 21.5K, 2.5V output from channel 1 of ADP5052 is achievable. Please confirm that there are no unintended consequences here. Also, I worry about signal integrity when routing differential pairs through standard 0.1" pin headers. Is this a valid concern for my frequencies of interest (50 ~ 200MHz)? I appreciate your input.
  3. Hi, I would like to know what IO standard would I use if I want to input a differential signal to two adjacent PMOD headers on PMOD JB. This differential signal will be an input to a buffer on the FPGA. The current xdc file on github uses LVCMOS33 as a default standard as shown below. set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { Input_data }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] Would it be fine if I use LVCMOS33 or should I use another IO standard and if so which one should I use. I am using the Arty A7 100t board. Thank you
  4. Hello, I am trying to implement LVDS (1.2V nominal) using the Digilent Arty-S7 25 board. The schematic shows that the JA and JB Pmod connectors have 4 diff. pairs per connector. However, it looks like VCCO (the power supply for this I/O bank) is tied to 3.3V. To my knowledge, there is no differential I/O protocol that uses 3.3V. Does this mean that JA and JB can't be used for differential pairs? (Wouldn't that negate the point of running the differential pairs in the first place?) Or do the pins just output the correct voltage when you implement the LVDS protocol? Please help! Thank you