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Found 3 results

  1. Hi, I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface. Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?
  2. Good afternoon everyone, I was wondering if someone implements a filter in an FPGA in VHDL language, but that was designed and generated by the FILTER DESIGN HDL CODER tool (Matlab). To help me with some doubts. Thanks
  3. Hello, We are a company based in Pittsburgh, Pennsylvania, and we are looking for a contractor who has experience with FPGA design work. Thank you.