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Hello Digilent! I am currently trying to build FPGA logic to match the DEPP standard. However, when looking through the Adept SDK documentation, and in particular the "Digilent Asynchronous Parallel Interface (DEPP)" standard, I noticed that the timing diagrams on pages 3 and 4 for both data and address transactions depended on the address strobe line. Is this a typo? Shouldn't the data write and data read transactions be dependent upon the DSTB or data strobe line? Thanks! Dan