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Found 19 results

  1. I have been following your "low_level_zmod_adc_dac" demo tutorial found at https://reference.digilentinc.com/reference/programmable-logic/eclypse-z7/low_level_zmod_adc_dac, and I believe there may be a typo. I copied the TCL commands to check out the project and received a "couldn't read file" error in the TCL command window. The command provided in the demo tutorial is set argv ""; source digilent-vivado-scripts/digilent-vivado-checkout.tcl, with all hypens. However, the scripts from the GIT digilent-vivado-scripts GIT project use underscores in the tcl filenames. Note that the exa
  2. Hi FPGA Gurus ! This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! 😃 Question 1 (solved): I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /* * These constants refer to the configuration of the hdmi_out core parameters. */ #define pFrame 0x49000000 //frame base address #define xcoFrameMax 1280 //frame width #define ycoFrameMax 720 //frame height #define lLineStride 0x800 //line stride
  3. When looking at the Cora example projects I can not find the xpr file. The demo's reference a <archive extracted location>/vivado_proj/ directory. /vivado_proj does not seem to exist. Any ideas where I can find it? https://github.com/Digilent/Cora-Z7-10-Basic-IO or https://github.com/Digilent/Cora-Z7-10-XADC Thanks
  4. Tom G

    Genesys 2 HDMI demo

    Does anyone have the Digilent HDMI demo running on the most recent Xilinx IP cores / Vivado 2019.2? Upgrading the IP cores (necessary because I don't have a license to the old ones) seems to result in the bitstream generation failing and a ton of error messages that I can't see how to resolve. Any help much appreciated.
  5. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current v
  6. I'm trying to run the Zybo Z7 Pcam 5C Demo... i'm really new at this, the instructions say: ********************************************************** To generate the project: 1. Open Vivado 2017.4 2. In the tcl console, type "cd [this directory]/proj" and press enter. 3. Type "source ./create_project.tcl" and press enter to generate the block design for the project. To run the demo from SD card: 1. Copy bin/BOOT.bin to the root of your SD card. 2. Set the boot jumper on the Zybo Z7 to SD. 3. Insert the SD card into the Zybo Z7 and power it on. **********
  7. Hello, I am using Vivado 2018.2 i downloaded "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project in original project "part" option is choosen then I created a new vivado project i choose "board" option and i created same block design with "Zybo-Z7-20-Pcam-5C-2018.2-*.zip" demo project. I inserted same IP blocks and made connections. I did synthesis and implementation succesfully but when i exported to SDK and i tried to boot from SD card (i used hello world template) i did not see anything on terminal but when i am trying to export original project to SDK not which i create, then i can see he
  8. Dear Experts, The hdmi in to vga out demo project gives perfect resolution at 1080p settings. But, wherever I try to set other resolution as I need 720p, it gives me extended resolution. Is there any option that I can fix it at 720p? Coz the monitor I want to use for output doesn't support Full HD (1080p) resolution. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start Regards- Shuvo
  9. Hi I have a general question about how to try out tutorials, demos, and just how to look at a project folder. When I open a tutorial/demo/project that I download from github, I always see a bunch of folders with the same names: hw_handoff, proj, repo, sdk, src, among other things. Can someone please explain these names, and maybe names of other folders that I may see in other projects? Are the contents of these folders dependent on each other? Can I implement the project with just one? How do I use these folders? Thanks
  10. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negati
  11. Dear experts, I am actually new in this field and have a very few experience with zybo board. I have implemented the zybo_hdmi_in_demo which is required for my master thesis. Output video streaming at the VGA monitor shows a cropped part of my input video source. What should I do now? And can I use other HDMI source rather than my PC? And what is the preferred input HDMI video resolution? any kind of support or suggestions is highly appreciated.
  12. I'm wondering where do we find the source for the Cmod A7 Stopwatch demo? One the demo's page (https://reference.digilentinc.com/cmod_a7/cmod_a7/cmod_a7_stopwatch/start) I can only find links for the bit and bin files. Since this is the only one of the Cmod A7 demos that exercises the pins (as opposed to on-board features), it would be useful to have a known-good demo project to modify. Thanks!
  13. Hello, I'm trying to build this demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start and I have error while generating project (after run in console "source ./create_project.tcl") WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2 ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART' Please help Any idea why it happens? I have: Windows 8.1 Vivado 2016.4 HLx WebPACK
  14. I'm trying to run the HDMI-in and HDMI-out demos on my ARTY Z7 board and I'm having problems building the SDK side of the projects. The problems are the same for both of these projects. After importing the project in the SDK I get the following error: 09:07:45 ERROR : The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace. As a result, this BSP will not build properly. To fix this error, please import the associated hardware project or recreate a new BSP targeting an existing hardware platform. Upon building the project I get the following errors (so
  15. Hi all FPGA fans and gurus ! First off : I am a total noob at all those FPGA and electronics things. So please be patient with me Now, for my problem : I recently got a second hand Atlys Board. My goal is to program it so that it can realtime rotate some hdmi input to its output. The input is a [email protected] signal. The goal is to rotate it and output a [email protected] signal (640 pixels fit in 720, with black borders 40 pixels wide each side). So, as I don't know anything about FPGA programming, I downloaded the following EDK HDMI demo on the Atlys resource page, I thought it wou
  16. Hi All, I am trying to use the ChipKITCAN library. This is a wrapper for the microchip CAN network library. I am using the legacy peripheral library to do this. I have been able to build the demo using MPIDE but I haven't been able to run it successfully. Is there any clear set of steps to run the demo in a chipkit max32? Also, I have been able to build this using Arduino IDE but running in the same issue. Any help is appreciated.
  17. Hi, I want to test ethernet of my Zybo board. Referring to xapp1026,I got how to use sdk to build a project,however,is there any demo to test ethernet in detail? For example,how to test the communication between board and PC? If I use standalone mode,then what should I do ?and for embeded system? Regards, Sophia
  18. I bought a Nexys™4 Artix-7 FPGA a while ago and I turned it on today. I was waiting for the user demo that comes pre-installed to say PASS but instead this time is says "Fail 2" "see doc". what does this mean? I cant find this anywhere in the document at all. Thanks alex
  19. Hello, I'm trying to get http://www.digilentinc.com/Data/Products/ATLYS/Atlys_AXI_Web_Server_Demo_v_1_02.zip to work on my Atlys board but I'm running into errors in SDK. After I clean & build, the elfcheck passes: 10:39:52 **** Incremental Build of configuration Debug for project Atlys_Webserver_Demo **** make all 'Building file: ../src/additional_sf_ops.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunc