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Found 17 results

  1. Hello! I have an example design where I am writing values into a BRAM. I have confirmed through simulation that the values are stored correctly. However, what I want to do is to confirm that the values are saved running on hardware as well? I have been trying to debug using the TCF debugger and trying to check the Memory window on the uB but I am not getting anything sufficient or understandable. What should I do if I want to, for example, test my memory through the MicroBlaze, shall the D-cache and I-cache be enabled? Could you give me any suggestions or examples on how to confirm the content without using simulation? My initial goal is to start with a BRAM and then go on with an SDRAM as well. regards John
  2. I have been trying to use the MIG in Vivado to work with the Xilinx Arty on-board DDR3 chip. So far I have gotten nothing but errors and dead ends from tutorials and documentation. Does anyone know of the best and simplest way to communicate with the RAM?
  3. Hello! I cannot debug the DDR3 outputs/inputs. I get the following error message. Bus interface connection '/mig_7series_0_DDR3' is connected to interface '/mig_7series_0/DDR3' with VLNV, which is not debug-able by System ILA IP. HDL attribute 'DEBUG' will not be set to this bus interface connection. Could anybody help me with this? I am going to check if my 640x480 picture is saved in the ddr3 but I have to use the ILA which does not work atm. regards, John
  4. blueshark

    DDR3 Usage

    Hello there, for six month I am learning VHDL, FPGA and related with an Artix-7 FPGA Development Board [1]. Now I am trying to access the onboard DDR3 memory for reading and writing. For convenience I try to avoid writing my onw DDR3 Interface, so I was looking at several IP cores. My plan was configuring a suitable IP core and create an HDL Wrapper, so that I can access it from my VHDL code. I tried the Memory Interface Generator, but on the other end it has an AXI Slave Interface. So it seems that one interface I have to implement by myself. Is there any simple solution or way, how to use DDR3 Memory? Something like Block Memory Generator provides. This interface is simple, which is easy to use for a beginne like me. blueshark [1]
  5. Hello! I have been investigating how multiple clock domains work and how you can send data ASAP from a camera module to a SDRAM (taking a pic). I am currently using a Nexys-Video and a Zed board and wonder if I could get some tips. The problems I encountered during my research is: -The picture I take has to be stored ASAP, meaning I have to use the mig7 interface for the SDRAM and HDL code. However this will be hard since it requires me to understand how the MIG7 works and thus writing a HDL that is adjusted to work with it. - What is the maximum frequency of a micro blaze? Using the micro blaze would be easier for me since I can directly write and read to/from the SDRAM using the peripheral libraries. However, the maximum clock frequency of a MB processor is not so much thus making that choice a bottleneck. - How should the communication between the camera and the SDRAM work? My initial idea was to use a buffer (BRAM) and store my picture there and then somehow do pipelined reading using the micro-blaze. Or alternatively, to send bytes to the micro-blaze directly without using a buffer. However I don’t really know if that is a good idea since the camera and the micro blaze work on different clock frequency levels. Would be glad if you could help me on the way. Regards, John
  6. Hello! I'm newbie in xilinx, and I have one more problem with microblaze with ddr3. I want to have access to DDR3 memory in my MB processor, without processor caches. I implement some design, write very simple code: #include "xparameters.h" int main() { int a = 0; for(;;) { a++; } return 0; } and I can't start debug ... When I start debug, it don't stay at main (but, thread is still running). When I pause it, I see in disassembler what processor stays at _hw_exception_handler In attach you can see system, linker mapping, and problem.. Please help me.
  7. I'm working on some embedded software on the Arty board and programming in Microblaze. When I try to allocate an array of sixteen-bit numbers, length 512, it works just fine, but the same array set to length 1024 causes malloc to return NULL. After some experimentation and testing, I believe this is because the Microblaze processor has run out of internal memory. However, the Arty board is supposed to have 256MB of DDR memory. An interface to the memory already existed in my block diagram (copied from Getting Started With Microblaze with some PMods added), so I assumed that the DDR memory was already being used by the Microblaze processor, but 256 MB of memory shouldn't be struggling to deal with a 2KB array. (Outside of the allocated array, the program is very small.) Is there something special I need to be doing to access the DDR memory from inside Microblaze?
  8. Hi, I have a simple design. In an ARTY board, I need to read from ddr3 initialized in SDK and write to pmod constantly in a loop. What is the recommended way to do this? Do I need to use the DMA? Is there a reference design for ARTY board? Thanks
  9. Hi there I just want to verify how to store float values in DDR3 of zed board. I have written a small code, but when i read from memory, i am not getting the correct answer. Is it correct? can someone help me? #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_io.h" #include "xparameters.h" #define DDR_BASEADDR 0x01000000 int main() { init_platform(); int i; float img[5] = {11.2345 ,17.2135 ,11.65 ,18.543 ,7.6789}; for (i = 0; i <5; i++) { Xil_Out32(DDR_BASEADDR+(i*4),img); } cleanup_platform(); return 0; }
  10. Hi there, I have a zed board and i want store data into DDR3 for my application. The data is in .txt file. I stored it. But when i am reading the data , its giving the wrong values. Can someone help me? firstly, Is it correct what i am doing? thanks in advance
  11. vishnu

    DDR3 configuration

    Hello Everyone, This is Vishnu , FPGA Design Engineer. I need help from you, in my project I need to get data into DDR from camera and has to given for another data processing module. Here I have some doubts regarding storage . 1) As camera is line scanning camera , Is it possible to store line information from camera (line-by-line) and to access it full line-by-line directly.(data is of 12 bit). 2) How many cycles will be delayed if configuration is done with Microblaze . 3) Help me out some links for the configuration to do in customized version. Thanks in advance. Regards Vishnu
  12. Hi, I am very new at field of FPGA. Now I am working Genesys2. I have to control DDR3 memory. I find some examples in Digilent site for DDR3 using microblaze processor. But, in my case I don't have to use microblaze processor. I have to send some fixed value through the DDR3 memory like 8-bit data (X'FF') i.e. I will write that data into the Genesys2 DDR3 memory and readout the data from the memory. I already go through Xilinx manual ug_586 . But still it is not clear to me how to start coding for the DDR3 memory. My questions are: 1) Is it possible to have example code without using microblaze processor for DDR3 memory? Or any suggestion for starting code to control DDR3 memory. Actually, I have do it in any way. So any helpful suggestion will be appreciated. Thank you.
  13. I'm trying to figure out which DDR3 memory chip is on the Arty. According to the schematic, the Arty has the MT41K128M16JT-125K DDR3 memory chip. According to the MIG project file I downloaded, however, the chip is the -15E. The difference between the two chips is significant, as one runs at a 1600 rate, whereas the other runs at 1333. The MIG project file appears to be designed for the 1333 data rate, but this would be inappropriate if the chips is the -125K chip. Can you tell me which chip is actually on the Arty? Thanks! Dan
  14. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem
  15. The MicroBlaze related examples have the DDR3 running at 166.667MHz and the MicroBlaze running at 83.333Mhz Can the MicroBlaze be run at 100MHz or higher on the ARTY board? Can the DDR3 be clocked faster than 166.667Mhz on the ARTY board?
  16. I´m learning the arty board, so i just want to know which is the max frequency for write/program on the DDR3, using vivado and microblaze
  17. AlbertoEnablia


    I would ask you if it is possible to have the Vivado or ISE Core Generator Project of a typical MIG configuration for DDR3 interface of your NETFPGA-1G-CML board. Thanks in advance.