Search the Community

Showing results for tags 'ddr2'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions


  • Community Calendar

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 5 results

  1. Hi, I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface. Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only supported in DDR3 and DDR4. Is there any equivalent way to do that?
  2. I'm writing a cpu on Nexys 4 DDR, but I have a problem: The DDR2 memory on Nexys4 will be reset whenever a new .bit file is written to the FPGA. I have already generated two .bit files. One is to write instructions and data to the DDR2 memory, and the other is the cpu program. What should I do to make the DDR2 memory remain the same even after it's programmed? Thank you!
  3. Hi all. I would like to ask you a question regarding the RAM/DDR controller of the Nexys4DDR. I would like to access (IP parameters in the MIG as in ) the ddr memory whose component is shown below using a 16b width data. For this, if I am correct, the address is handled RANK_BANK_ROW_COLUMN. So I do not understand why in the provided code from Mihaita Nagy they create the user_interface address like these mem_addr <= ram_a_int(26 downto 4) & "0000"; Here, mem_addr has 27b width. Similarly, I wonder why in the ram control the mask and the read data uses the following LSB and not the MSB of the address: case(ram_a_int(3 downto 1)) is when "000" => if ram_ub_int = '0' and ram_lb_int = '1' then -- UB ram_dq_o <= mem_rd_data(15 downto 8) & mem_rd_data(15 downto 8); ... Would not it be more sense to store the 16b words contiguously, starting at the address 0? and if so, how would the vhdl code look like? Thank you very much for your time, and regards. The component used looks like component ddr_xadc port ( -- Inouts ddr2_dq : inout std_logic_vector(15 downto 0); ddr2_dqs_p : inout std_logic_vector(1 downto 0); ddr2_dqs_n : inout std_logic_vector(1 downto 0); -- Outputs ddr2_addr : out std_logic_vector(12 downto 0); ddr2_ba : out std_logic_vector(2 downto 0); ddr2_ras_n : out std_logic; ddr2_cas_n : out std_logic; ddr2_we_n : out std_logic; ddr2_ck_p : out std_logic_vector(0 downto 0); ddr2_ck_n : out std_logic_vector(0 downto 0); ddr2_cke : out std_logic_vector(0 downto 0); ddr2_cs_n : out std_logic_vector(0 downto 0); ddr2_dm : out std_logic_vector(1 downto 0); ddr2_odt : out std_logic_vector(0 downto 0); -- Inputs sys_clk_i : in std_logic; sys_rst : in std_logic; -- user interface signals app_addr : in std_logic_vector(26 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_wdf_data : in std_logic_vector(127 downto 0); app_wdf_end : in std_logic; app_wdf_mask : in std_logic_vector(15 downto 0); app_wdf_wren : in std_logic; app_rd_data : out std_logic_vector(127 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_sr_req : in std_logic; app_sr_active : out std_logic; app_ref_req : in std_logic; app_ref_ack : out std_logic; app_zq_req : in std_logic; app_zq_ack : out std_logic; ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; -- device_temp_i : in std_logic_vector(11 downto 0); -- not used, inside the core init_calib_complete : out std_logic); end component;
  4. Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_complete = '1' then sig_en <= '0'; sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15 downto 9) <= (others => '0'); if commnd = CMD_WRITE then aState <= stWriteComd; elsif commnd = CMD_READ then aState <= stReadComd; end if; end if; when stReadComd => sig_en <= '1'; sig_cmd <= CMD_READ; --LED(9) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stWriteComd => sig_en <= '1'; sig_cmd <= CMD_WRITE; --LED(10) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stComdAcep => if sig_rdy = '1' then sig_en <= '0'; --LED(12) <= '1'; if commnd = CMD_WRITE then sig_wdf_wren <= '1'; sig_wdf_end <= '0'; sig_wdf_data(12 downto 0) <= "1010101111111"; aState <= stWriteData; elsif commnd = CMD_READ then aState <= stWaitRead; end if; end if; when stWriteData => if sig_wdf_rdy = '1' then sig_wdf_wren <= '1'; sig_wdf_end <= '1'; --LED(13) <= '1'; sig_wdf_data(12 downto 0) <= "1010101010101"; aState <= stWaitAct; end if; when stWaitRead => if sig_rd_data_valid = '1' and sig_rd_data_end = '1' then --LED(14) <= '1'; aState <= stWaitAct; data_out <= sig_rd_data; end if; when stWaitAct => sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15) <= '1'; if ready = '1' then aState <= stInit; end if; end case; end if; end process;
  5. Hi, I am trying to interface ddr2 SDRAM with microblaze using PLB bus. I also used central DMA controller. I have problem of generating UCF file for memory based on Atlys board. Any one can help me? Regards