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Found 6 results

  1. Hi all, I have created a block design in vivado,and generate bitstream successfully.Everything seems to be successful,and then i export hardware and create an application project with "Hello world" template,and i did not change anything. But when i try to program FPGA, i get the following error messages. " ERROR: [Updatemem 57-153] Failed to update the BRAM INIT strings for ./.../*.elf and ./.../*.mmi " I'm pretty sure that i have selected the bitfile that was generated earlier. And here is my block design ,any suggestions?
  2. Hi, I impelemnted a design composed of a softcore processor (RISC-V based), on a Nexys 4 DDR (Nexys A7) board. The software is stored in the DDR2 Memory. The software accesses the DDR2 memory through a controller interface. Now, I'd like to add an Audio IP that can fetch some audio samples, stored in a specific location (by the processor) in the DDR2 memory, and feed them to the audio output. However, since the interface is taken by the processor, is there a way to use that interface by the audio driver too? I read about something called the Ping Pong PHY, but apparently it is only
  3. I'm writing a cpu on Nexys 4 DDR, but I have a problem: The DDR2 memory on Nexys4 will be reset whenever a new .bit file is written to the FPGA. I have already generated two .bit files. One is to write instructions and data to the DDR2 memory, and the other is the cpu program. What should I do to make the DDR2 memory remain the same even after it's programmed? Thank you!
  4. Hi all. I would like to ask you a question regarding the RAM/DDR controller of the Nexys4DDR. I would like to access (IP parameters in the MIG as in ) the ddr memory whose component is shown below using a 16b width data. For this, if I am correct, the address is handled RANK_BANK_ROW_COLUMN. So I do not understand why in the provided code from Mihaita Nagy they create the user_interface address like these mem_addr <= ram_a_int(26 downto 4) & "0000";
  5. Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_co
  6. Hi, I am trying to interface ddr2 SDRAM with microblaze using PLB bus. I also used central DMA controller. I have problem of generating UCF file for memory based on Atlys board. Any one can help me? Regards