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  1. Hi, I want to develop a simple subsystem that is shown on the picture below. Basically, I need one producer that would generate a picture(s) and one consumer that would display the picture. The consumer is easier part, it's VGA block that reads the pictures from the memory. I want to use a bigger resolution, so I cannot use BRAM and I have to go for DDR. I'm planning to use MIG for this job. The question is whether I can configure DDR as a dual-port ram (one port for generator and one port for consumer). Is it possible? If not, I think that I have to go with multi-master bus, so the consu
  2. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code,
  3. Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I
  4. Hello, I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here: But there doesn't appear to be any constraints for the DDR3. I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- #  For DDR constraints please refer to our website #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Where can I find the pin, lev
  5. Hello, I am wondering what is the best way to share a big chunk of memory between two cores of Arty-Z7-10? Note that I have already gone through the XAPP1079 of Xilinx, however this tutorial does not really share the DDR memory between two cores. It only uses OCM to share a semaphore between two cores, so two cores can share the terminal. To give you more detail on what my goal is: I want to read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do with OCM). Followin
  6. Hi, I am trying to get the Microblaze working with the PS hand in hand, i.e. some program is running on the PS and some of it tasks should be outsourced to the Microblaze. My question is how do I need to connect the Microblaze with the PS such that this communication possible ? Some guide/tutorial would be awesome. Thanks!
  7. OK... I've pored over the forums, and found many questions tangentially related to my topic, yet cannot figure out the answer to my question. I'm using the *original* Digilent Zybo board, i.e. it has a VGA port. I've used one personally for a while now, but I'm now doing a project at work on a new Zybo. I cannot, for the life of me, get the DDR to be configured to work properly. I have tried every which way... including a custom memory part but it is all to no avail. I tried to get around this by using OCM, and it works, but then I could not get the QSPI to flash with my execute
  8. Hello, i have successfully implemented a hardware design smilar to this one. I am able to use the PL as a bridge between the PS and DDR. I would also like to trace the exact addresses that are being carried by the s2mm/mm2s between the ddr and dma. Is it possible to assign them some addresses(e.g. in the address editor in vivado) and track them from the OS running on the board ? Thanks.
  9. Hello, is there an IP that can track memory reads and writes and, eg. output them to a minicom (program thisvia XSDK)? I have tried this works fine, all tests run through. But I don't really know where to look for an approach to this. Is it possible to trigger something within the sdk when a memory access is happening ? Thanks
  10. Hello everyone, I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it. Thanks for your time.
  11. Hello, so I followed this axi-dma tutorial and everything looks pretty fine. Now, this tutorial only goes to running a HelloWorld application inside de XSDK. I would like to know how t write something to DDR and how to read something back (specifying addresses e.g.)? To be precise this is how the actual design looks like I would really appreciate some sample C code of how to instantiate (?) the AXI Slave/Master ports to be able to read something from the DDR. Thanks !!
  12. Hi, i would like to just be able to read memory addresses from RAM on my Zybo Zynq -7000. I have read some interesting articles including this one I followed every step but I'm still missing the part where i can e.g. just read an address print it out (and write it back?). If this could be done with the SDK in c/c++ it'd be awesome . Could anyone recommend me some literature or is there a tutorial which i can follow to understand this better ? Thanks in advance
  13. Weevil

    Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dd
  14. hello, I used the zybo_hdmi_in as reference for my project. I struggled with the VDMA. After some modifications (added image sensor as input) It seems so I have my program code overlapping with the DDR memory of my frame buffer. I found that my design works once I added an offset to the DDR_0_BASEADDRess. Without the offset the VDMA gives an address encoding error. I increased the offset until it works. Now, the printf's are no longer showing... Looking into UG585 (TRM) the VDMA is definetely within the address range 0010_0000 to 3FFF_FFFF and there seem no overlap.
  15. Dear Expert I am working on Petalinux 2015.4 and Zedboard. I want to have a contagious 4 MB block of DDR to communicate with PL and have the physical address of the its Base. -Can I have this much memory allocated? -How can I get physical address of the memory? Regards
  16. Hello. I want to get data from DDR directly. So I connect DDR_DQ, DDR_DQS, DDR_clk as below f1. but after I synthesize this, I find there is no connection as below f2 Is there any better way for it? I need help.
  17. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  18. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post. And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors. I want to use 7-segment to display the data that read from the DDR, however, it didn't work. This is my top module. Could someone help me with this issue? Thanks, Shaw test_dd
  19. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter i
  20. Hi, At the start of the year I purchased a Nexyss 4 DDR board from Digilent. I hadn't used it until a few weeks ago, but now am using it for a university project. However, I have discovered two issues with the board while using it. 1. Switch 3 (of the sliding switches), is faulty. The switch will sometimes read as "on", even when the switch is in the "off" position unless it is actively pulled back. I can verify that this is not a coding problem because it happens when the device boots into the default program (loaded by digilent) and all other switches work. 2. Transistor
  21. I have observed, what to me is, unexpected behavior in regards to the power consumption of the ZedBoard (Zynq-7000) when a processing core accesses the on board DDR memory in certain situations. I have performed a number of tests were I monitor the power consumption of either the A9 core with DDR or a softcore Microblaze with DDR. For both setups I have found cases where the power consumption of the board when actively running a program that frequently accesses DDR is lower than when the processor is sitting idle. This does not make sense to me as I would expect the power when active to be
  22. Hello, I am using Xilinx ISE 14.7 I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end. I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons. I started Translate and Map, Translate returned a lot of messages like: And Map returned: I found there a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the
  23. Hi, IN the present 512MB x32 DDR3 RAM , hoe much DDR RAM i can use for data storage in SDK , as given in lscript.ld file. Up to wat range the size of DDr can be set. How to access that memory in C (SDK) . if this is bot possible ten ow can i access Block RAm in SDK for PS usage not interm of PL.
  24. From the album: - Firmware for capturing HDMI and DisplayPort via USB and Ethernet

    __ _____ __ _______ ___ __ _________ / // / _ \/ |/ / _/ |_ | / / / / __/ _ ) / _ / // / /|_/ // / / __/ / /_/ /\ \/ _ | /_//_/____/_/ /_/___/ /____/ \____/___/____/ alternative Copyright 2015 / EnjoyDigital [email protected] Alternative HDMI2USB gateware and firmware based on Migen/MiSoC [> Supported Boards ------------------ This firmware is supported on the following to boards; * Digilent Atlys - The original board used for HDMI2USB prototyping. Use `BO

    © MIT

  25. I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren