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Found 28 results

  1. Hi, I want to develop a simple subsystem that is shown on the picture below. Basically, I need one producer that would generate a picture(s) and one consumer that would display the picture. The consumer is easier part, it's VGA block that reads the pictures from the memory. I want to use a bigger resolution, so I cannot use BRAM and I have to go for DDR. I'm planning to use MIG for this job. The question is whether I can configure DDR as a dual-port ram (one port for generator and one port for consumer). Is it possible? If not, I think that I have to go with multi-master bus, so the consumer is another master on the bus... Other memories that Nexys A7 has are too small (and I guess also to slow). Any help is appreciated. Thanks, Dannny.
  2. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  3. Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I'm not sure if I should use the BRAM module, the DDR, SRAM... What are the differences of these components and which one would you suggest to use? Finally, would you have a tutorial that goes through the different steps of the implementation? Thanks a lot, NotMyCupOfTea
  4. SeanS

    Genesys 2 DDR Constraints

    Hello, I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here: But there doesn't appear to be any constraints for the DDR3. I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- #  For DDR constraints please refer to our website #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Where can I find the pin, level, and timing constraints for the DDR3 peripheral interface? -Sean
  5. Hello, I am wondering what is the best way to share a big chunk of memory between two cores of Arty-Z7-10? Note that I have already gone through the XAPP1079 of Xilinx, however this tutorial does not really share the DDR memory between two cores. It only uses OCM to share a semaphore between two cores, so two cores can share the terminal. To give you more detail on what my goal is: I want to read a big chunk of data (something in oder of 15 - 30 MB) on CPU#0 and put that into DDR memory, and then let the CPU#1 know when I am done via a flag (which I know how to do with OCM). Following this, I want CPU#1 to access the data that CPU#0 put in DDR and write it to the SD card, while CPU#0 starts to read the 2nd chunk of data. To do this, it is clear that I need to modify the ldscript of two cores, so they share part of the memory. I wonder if anyone has done such kind of thing before and have any suggestion? Regards, Mahdi
  6. Hi, I am trying to get the Microblaze working with the PS hand in hand, i.e. some program is running on the PS and some of it tasks should be outsourced to the Microblaze. My question is how do I need to connect the Microblaze with the PS such that this communication possible ? Some guide/tutorial would be awesome. Thanks!
  7. OK... I've pored over the forums, and found many questions tangentially related to my topic, yet cannot figure out the answer to my question. I'm using the *original* Digilent Zybo board, i.e. it has a VGA port. I've used one personally for a while now, but I'm now doing a project at work on a new Zybo. I cannot, for the life of me, get the DDR to be configured to work properly. I have tried every which way... including a custom memory part but it is all to no avail. I tried to get around this by using OCM, and it works, but then I could not get the QSPI to flash with my execute in place linker script... something I've done several times for work on the Zedboard. Can someone please help me with the correct DDR configuration so I can get this out from over my head? I'm attaching the current DDR configuration... any help is greatly appreciated. Thank you!
  8. Hello, i have successfully implemented a hardware design smilar to this one. I am able to use the PL as a bridge between the PS and DDR. I would also like to trace the exact addresses that are being carried by the s2mm/mm2s between the ddr and dma. Is it possible to assign them some addresses(e.g. in the address editor in vivado) and track them from the OS running on the board ? Thanks.
  9. Hello, is there an IP that can track memory reads and writes and, eg. output them to a minicom (program thisvia XSDK)? I have tried this works fine, all tests run through. But I don't really know where to look for an approach to this. Is it possible to trigger something within the sdk when a memory access is happening ? Thanks
  10. Hello everyone, I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it. Thanks for your time.
  11. Hello, so I followed this axi-dma tutorial and everything looks pretty fine. Now, this tutorial only goes to running a HelloWorld application inside de XSDK. I would like to know how t write something to DDR and how to read something back (specifying addresses e.g.)? To be precise this is how the actual design looks like I would really appreciate some sample C code of how to instantiate (?) the AXI Slave/Master ports to be able to read something from the DDR. Thanks !!
  12. Hi, i would like to just be able to read memory addresses from RAM on my Zybo Zynq -7000. I have read some interesting articles including this one I followed every step but I'm still missing the part where i can e.g. just read an address print it out (and write it back?). If this could be done with the SDK in c/c++ it'd be awesome . Could anyone recommend me some literature or is there a tutorial which i can follow to understand this better ? Thanks in advance
  13. Weevil

    Streaming FFT data

    Hi all, i am working on my first larger project and try to stream data from my FPGA logic over usb to my computer. I generate a 16bit sine wave with a dds-compiler, doing an FFT and now i want to send the result of the FFT to my computer. Attached i build up a microblaze system with an DMA IP and DDR connection using the arty board. How i can now stream the new generated result of the FFT over the uart port to my computer using the Xilinx SDK, btw. is there a similar example available? (uartlite IP is connected to the microblaze processor) Additional, is the connection between the dds-compiler over the Stream-Data-FIFO to the FFT right?
  14. hello, I used the zybo_hdmi_in as reference for my project. I struggled with the VDMA. After some modifications (added image sensor as input) It seems so I have my program code overlapping with the DDR memory of my frame buffer. I found that my design works once I added an offset to the DDR_0_BASEADDRess. Without the offset the VDMA gives an address encoding error. I increased the offset until it works. Now, the printf's are no longer showing... Looking into UG585 (TRM) the VDMA is definetely within the address range 0010_0000 to 3FFF_FFFF and there seem no overlap. Can anyone suggest me a good document where I can learn more about Zynq memory mapping, and observe problems like stack overflow etc? thanks
  15. Dear Expert I am working on Petalinux 2015.4 and Zedboard. I want to have a contagious 4 MB block of DDR to communicate with PL and have the physical address of the its Base. -Can I have this much memory allocated? -How can I get physical address of the memory? Regards
  16. Hello. I want to get data from DDR directly. So I connect DDR_DQ, DDR_DQS, DDR_clk as below f1. but after I synthesize this, I find there is no connection as below f2 Is there any better way for it? I need help.
  17. Question to experts: What is the fastest way for saving continuous data coming from PL on Zynq without requiring the processor you would recommend? The data rate is expected to vary in the range 4-8 MB/s. Preferred processor operational mode is standalone. Options considered so far are BRAM, OCM and DDR3. All of these options seems require custom HDL coding to interface Zynq memory. Before comitting to such effort I'd like to hear opinions from the community. Thank you!
  18. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post. And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors. I want to use 7-segment to display the data that read from the DDR, however, it didn't work. This is my top module. Could someone help me with this issue? Thanks, Shaw test_ddr.v
  19. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!
  20. MattHollands

    Faulty Nexys 4 DDR?

    Hi, At the start of the year I purchased a Nexyss 4 DDR board from Digilent. I hadn't used it until a few weeks ago, but now am using it for a university project. However, I have discovered two issues with the board while using it. 1. Switch 3 (of the sliding switches), is faulty. The switch will sometimes read as "on", even when the switch is in the "off" position unless it is actively pulled back. I can verify that this is not a coding problem because it happens when the device boots into the default program (loaded by digilent) and all other switches work. 2. Transistor Q8 appears to not be functioning properly. By changing the voltage on the gate I should be able to change the SD cards VDD voltage from 0V to 3.3V, but in reality it is ~2.9V in the off-state and 3.3V in the on-state. I have verified that the gate is swinging from 0V to 3.3V as expected. Issue 1 is not a deal-breaker for me, but issue 2 is a significant deal-breaker as I need the ability to power cycle my SD card. Is this a common issue? It seems to me like this may be due to a faulty board. Matt
  21. I have observed, what to me is, unexpected behavior in regards to the power consumption of the ZedBoard (Zynq-7000) when a processing core accesses the on board DDR memory in certain situations. I have performed a number of tests were I monitor the power consumption of either the A9 core with DDR or a softcore Microblaze with DDR. For both setups I have found cases where the power consumption of the board when actively running a program that frequently accesses DDR is lower than when the processor is sitting idle. This does not make sense to me as I would expect the power when active to be the power of the core + the power to access DDR versus just the power of the core when idle. I will describe a few of the cases I have tested and what I observed. In all cases the “active” execution is running a version of GUPS (giga updates per second), a program that repeatedly accesses a random location in a memory array of a controllable size. Microblaze connected to DDR through the AXI HP0 and HP1 ports of the Zynq A9. The local microblaze memory is only used for startup code. All other code and data is in DDR. Case 1: Microblaze with 32 kB I and D caches running GUPs with a 192MB working set. When execution is complete the processor is put to sleep using the “sleep” assembly instruction Observation 1a: With the I cache enabled and D cache disabled (meaning all accesses to the array to be updated should go to DDR) the board level power consumption is 7.2% *lower* when actively running than when put to sleep. Observation 1b: When both caches are disabled (meaning all accesses should go to DDR), power consumption is 4.7% *lower* when actively running than when put to sleep. Case 2: Microblaze with 32 kB I and D caches running GUPs with 4k working set (meaning it should fit within cache). When execution is complete the processor is put in a loop that continuously accesses the same index of the data array and sums it into a dummy variable. Observation 2a: With both caches disabled (meaning all accesses should go to DDR), power consumption is 10.6% *lower* in the busy wait than when actively running. Observation 2b: With both caches enabled (meaning most/all accesses should hit in caches), power consumption is 1.1% higher when actively running than when put to sleep. Zynq-7000 A9 connected to DDR. Case 3: A9 running GUPs with 384 MB working set (meaning most data accesses should go to DDR). When execution is complete the processor is put in idle loop similar to Case 2. Observation 3a: With caches enabled power consumption is 0.1% *lower* during active execution than when in busy wait. These observations are counter to a number of my expectations from traditional systems. Expectation 1: A running core that misses in the cache (or has not cache) and must frequently go to DDR should have higher power consumption than a sleeping core. The former has the power of both the core and DDR while the latter has just the power of a sleeping core (and basic DDR refresh). Observations 1a and 1b are counter to this expectation. Expectation 2: A core hitting in a local cache should consume less power than a core that has to frequently access DDR. Observations 2a, 2b, and 3a are all counter to this expectation. I am interested in two items related to the above observations: A potential explanation for the above observations (I have a few possibilities, but none are easy to verify) Is there some setup or configuration setting that would produce more expected behavior in terms of power consumption? Thanks.
  22. Hello, I am using Xilinx ISE 14.7 I am trying to use SRAM to DDR Component which i've downloaded from nexys4-ddr-sram I've downloaded the UCF file for ddr pinout and added it to existing Nexys4DDR-Master.ucf at the end. I've created a instance of ramddr2xadc component and i've added IOs like switches and buttons. I started Translate and Map, Translate returned a lot of messages like: And Map returned: I found there a solution so i turned on the "Add IO Buffers" option. (I also tried to create instances of buffers and the result was the same). It removed these errors but now Map returned different error: I am using the ngc file from the /Netlist directory but i also tried to use files from /Source and i had the same problem. The solution for this issue on Xilinx Support tells me that i need to correct pin-out but I have downloaded official component so i think that it should work without any modifications. Could someone help me with this issue?
  23. Hi, IN the present 512MB x32 DDR3 RAM , hoe much DDR RAM i can use for data storage in SDK , as given in lscript.ld file. Up to wat range the size of DDr can be set. How to access that memory in C (SDK) . if this is bot possible ten ow can i access Block RAm in SDK for PS usage not interm of PL.
  24. From the album: - Firmware for capturing HDMI and DisplayPort via USB and Ethernet

    __ _____ __ _______ ___ __ _________ / // / _ \/ |/ / _/ |_ | / / / / __/ _ ) / _ / // / /|_/ // / / __/ / /_/ /\ \/ _ | /_//_/____/_/ /_/___/ /____/ \____/___/____/ alternative Copyright 2015 / EnjoyDigital [email protected] Alternative HDMI2USB gateware and firmware based on Migen/MiSoC [> Supported Boards ------------------ This firmware is supported on the following to boards; * Digilent Atlys - The original board used for HDMI2USB prototyping. Use `BOARD=atlys` with this board. * Numato Opsis The first production board made in conjunction with project. Use `BOARD=opsis` with this board.

    © MIT

  25. I'm about to play with the Nexys4 DDR "SRAM to DDR" component, but I've never used a MIG or a pre-existing netlist before. The instructions say "Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project." Can someone help me with an explanation on how to do this?! I'm using Vivado 2015.1. Thanks all! Warren