Search the Community

Showing results for tags 'dc'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL







Found 1 result

  1. I use a 10MHz clock and a 2-bit register to generate a 100 ns pulse at a frequency of 2.5 MHz(100 ns on, 300 ns off).The signal is output through an IOBFF into the pin JC1 (V15), which drives a 180 ohm resistor. According to the reference manual, JC is one of the 3 high speed PMODS, but despite this my rise and fall times are around 5-7 ns.The slew rate is set to "FAST" and the drive strength is set to "16".I want to decrease the rise and fall times to their absolute minimum value possible. The code for generating the pulse : reg [1 : 0] counter = 0; always @ (posedge clk) begin if(!reset) begin counter <= 0; gnd <= 0; pulse <= 0; end else begin counter <= (counter == 3)? 0 : counter + 1; //10MHz/4 = 2.5MHz , Period = 400ns pulse <= (counter == 3)? 1 : 0; //Pulse Length = 0.1us = 100ns gnd <= 0; end end The 'gnd' signal from the code is connected to the adjacent pin(JC2). I am also attaching images of the observed waveforms (both rise and fall) .The oscilloscope uses a BNC cable which is terminated at 50 ohms.To reduce measurement inaccuracy, I have tried to keep the ground wire short. The 180 ohm resistor,directly connected to the PMOD header, is being used to limit the current drawn from the pin.The fall time seems to be less than the rise time by about 1 ns, but it still is 5 ns, at least. What can I do to reduce the rise and fall time of an IO? From what I understand, using a higher frequency clock or an ODDR would have no effect as the switching should really be governed only by the DC characteristics. Thank you!