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Hey, In V4 version of the doc (and board?), http://digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V4.pdf (currently linked on Digilent website), the pin constraints for pcie-rx3_p, pcie-tx3_p, pcie-rx3_n and pcie-tx3_n are wrong, as they are the same as pcie rx/tx port 2 (see first half of page 19 of aforementioned pdf). In V3, https://www.digilentinc.com/Data/Products/NETFPGA-1G-CML/NetFPGA-1G-CML_rm_V3.pdf (found via Google), I discovered what might be the correct values - it would be nice if someone could confirm them as being right (page 19).