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Found 18 results

  1. Hello everybody, I want to implement a dac example into my fpga board (MYD-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.In other words, I try to implement LTC-2601 to 32 bit input. Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register (in this example slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only impulses. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some fluctuation in the wave. I leave my VHDL code below. Thank you. port( -- Users to add ports here output : out std_logic := '0'; -- User ports ends ); -- Add user logic here -- S_AXI_ACLK is the clock from Zynq-7000 Processing System IP. process(S_AXI_ACLK) variable index : integer := 0; variable counter: integer := 0; begin if rising_edge(S_AXI_ACLK) then case index is -- 4 Command Bits start when 0 => output <= '0'; when 1 => output <= '0'; when 2 => output <= '1'; when 3 => output <= '1'; -- 4 Command Bits end -- 4 Don't Care Bits start when 4 => output <= '0'; when 5 => output <= '0'; when 6 => output <= '0'; when 7 => output <= '0'; -- 4 Don't Care Bits end -- 16 Data Bits start when 8 => output <= slv_reg0(16); when 9 => output <= slv_reg0(17); when 10 => output <= slv_reg0(18); when 11 => output <= slv_reg0(19); when 12 => output <= slv_reg0(20); when 13 => output <= slv_reg0(21); when 14 => output <= slv_reg0(22); when 15 => output <= slv_reg0(23); when 16 => output <= slv_reg0(24); when 17 => output <= slv_reg0(25); when 18 => output <= slv_reg0(26); when 19 => output <= slv_reg0(27); when 20 => output <= slv_reg0(28); when 21 => output <= slv_reg0(29); when 22 => output <= slv_reg0(30); when 23 => output <= slv_reg0(31); -- Data Bits end when others => end case; if counter = 0 then index := (index + 1) mod 24; end if; counter:= ( counter +1) mod 20; end if; end process; -- User logic ends Note: This vhdl code is from my axi peripheral ip. The rest of the ports, entity, logic and etc is created by the ip itself. So I did not put them here.
  2. Hi everyone, After having succesfully managed to use de XADC of the Zybo Z7010 board as explained in this post, I am now trying to use a DAC Pmod (reference and documentation here). After having checked the documentation, I have tried to write the SPI connection to the DAC (please find the verilog file and simulation in the attached files). Note, that I have decided to set the l_dac signal to 0 to enable continuous output to an oscilloscope. The simulation seems to run well to me and to be in accordance with the documentation, however, the result is not satisfactory. Indeed, the signal I want to output is on 16-bits and the command "output = 16'b1111111111111111", which should give the max value does not reach it. Besides, when I ask to "output = 16'b1000000000000000", which should give half of the max signal, the output is almost zero. Finally, please find in the attached files the image I get on an oscilloscope when I input a sine signal with 0.5V offset and 1Vpp. Does aybody see what I am missing ? Don't hesitate to ask more details if needed. Thank you in advance, DAC_wiz_0.v DAC_wiz_0.sim
  3. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  4. Hello Technicians, I want to output a signal (FHSS_TX) in 2nd picture via a Pmod_DA module. In fact, I have the IP core of this Pmod (Pmod_DA3) , but I don't know how to merge the second design (my project in 2nd picture) with the first (Pmod & microbalze 1st picture) to out put my signal via the Pmod_DA3 , Kindly , find the attached pictures . Looking forward your supports . Thanks in advance.
  5. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 (24bit@48k), I2S output. DAC will be CS4390 (24bit@48k), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  6. Hi there, I've been using the Analog Shield with a UC32 for controlling and measuring different parameters in a physics experiment. I've noticed that for certain voltages, the DAC (and ADC) both have offsets on the order of 10 - 40 mV relative the value that they are being programmed to (or being feed to by a power supply). This offset seems to be random (in that it doesn't follow a specific trend), although it is consistent for the same ADC/ADC. I've also seen that the offset pattern is different for different DAC/ADCs on the same Analog Shield and I've also tested this on different Analog Shields and still seen this issue. This error seems to be much larger than the specified offset error for the DAC and ADC. Has anyone experienced similiar DAC/ADC offset issues with the Analog Shield? And has anyone developed any clever solutions/compensation libraries to deal with this to get more precise reading?
  7. CKV

    PMOD AD1 HDL codes

    Hello, can I get the HDL files for the PMOD AD1? Exactly I need code which can take the AD1 outputs D0 or D1 to HDL module and gives me the output has 12bit number. so that I can process these 12bit numbers in subsequent modules.
  8. ATIF JAVED

    ADC DAC SELECTION

    I want to interface DAC and ADC with some fpga evaluation board My requirement of ADC and DAC is following DAC input ->sampling_rate=2MS/s frequency=455khz ADC Input ->Signal bandwidth=400khz i have no problem of resolution So someone please guide me or refer me some models of adc and dac along with some FPGA evaluation board that complete my requirements . Also refer me if anyone know about some board that have build in adc dac along with FPGA Any kind of help in this regard would be much appreciable
  9. hello everyone I'm using fpga spartan 3 with DAC tl5615 which want really supported my purposes ( because i needed a DAC with higher resolution )i needed new DAC as i came across with pmod i2s here is the link https://store.digilentinc.com/pmod-i2s-stereo-audio-output/ so as i'm new with driving DAC (Primary IC is cs4344) i was wondering if anyone ever drive DAC before ? i search all the net but couldn't find anything best ethan
  10. i want to generate sine wave on dac (pmodda3)(http://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf)and i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  11. Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111 -- The right-most switch (SW0) defines the regime: working, fast (0) or "human", slow (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity pgnd is port( btnc : in STD_LOGIC; sysclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(3 downto 0); jb : out STD_LOGIC_VECTOR(3 downto 0) ); end pgnd; architecture pgnd of pgnd is signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0, pout: STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk, btnc) begin if btnc = '1' then count <= X"0000000"; elsif rising_edge(sysclk) then count <= count + 1; end if; end process; sclkp: process(sysclk, count, btnc) begin if btnc = '1' then sclk0 <= '0'; elsif rising_edge(sysclk) then if sw(0) = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0, btnc) begin if btnc = '1' then word_count <= "101000"; -- # 40 elsif rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process; -- Sync signal signal_syncp: process(sclk0, word_count, btnc) begin if btnc = '1' then sync0 <= '1'; elsif rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process; signal_shiftp: process(sclk0, word_count, sw, count2, btnc) begin if btnc = '1' then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; elsif rising_edge(sclk0) then if word_count = "101000" then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process; -- Sawtooth data modulation data_countp: process(sclk0, word_count, btnc) begin if btnc = '1' then count2 <= X"001"; elsif rising_edge(sclk0) and word_count = "101000" then count2 <= count2 + 1; end if; end process; -- Data transmission process spip: process(sclk0, word_count, btnc) begin if btnc = '1' then pout <= '0'; elsif rising_edge(sclk0) then -- Send the signal pout <= pdata(31); end if; end process; JB(0) <= sync0; -- SYNC JB(1) <= pout; -- DOUT JB(2) <= pout; -- Just duplicate DOUT JB(3) <= sclk0; -- SCLK led(0) <= sclk0 when sw(0) = '1' else -- show the real SCLK count(24); -- or indicate device is working on higher freq led(1) <= sclk0 when sw(0) = '1' else not count(24); -- Couple the other leds only if the frequency is "human" led(2) <= pout when sw(0) = '1' else '0'; -- DOUT led(3) <= sync0 when sw(0) = '1' else '0'; -- SYNC end pgnd;
  12. KevinS

    PmodDA3 Glitch

    We have a couple of DA3 modules connected to a pair of Xilinx Spartan 3 FPGAs. We are generating an audio ferquency baseband signal with at 200 ksps. Looking at the buffered output from the module we periodically see a sub-1us 500uV pulse approximately every 100 samples when outputting a small signal sinewave. Offsetting our sinewave by different amounts can make the problem either better or worse. The datasheet for the AD5541 DAC talks about a 'Digital-to-analog glitch impulse' that seems to explain our unwanted pulse. We have crudely filtered out this pulse with an 18pF cap from the DAC output to GND. This does not seem to cause any problems at our relatively low baseband frequency. Is there an accepted method of dealing with these unwanted pulses? Would it be possible to add a position on the Pmod board for a filter to be added?
  13. Hi Friends, We are using the analog shield for measuring some analog feedbacks but we find out there is 0.65V off set for each reading chanels and also the open circuit voltage is 2V. Can you tell us what is wring in there?
  14. Hi, I have a question from a customer. Can anyone help? Would it be possible to do some simultaneous sampling with the analog discovery board with a sample rate of e.g. 500khz or is it time limited due the internal buffer length? Would it be possible for the ADC and DAC at the same time?
  15. Hey guys, I'm currently trying to spec a project using the Uno32 with the pmod shield. The pmod I would like to use is the DA4 digital to analog converter. I've noticed that in Diligent's reference section there is an example code section for the pmodDA1 which gives a zip file including examples, a library, and a library manual for using the DA1. However such resources don't exist for the DA4. Does anyone know if that library be necessary for using the pmodDA4, or where I can find some examples of using it? I'm not new to microcontrollers, but I am new to pmod... Any help would be appreciated! Thanks!
  16. I’m a PhD student working in a mechanics laboratory in France (LMT Cachan) and one of the goals of my thesis is to control a hydraulic testing machine using digital image correlation techniques. In order to do this, I need to take a photo of a sample, process it, extract 4 parameters and send them to the testing machine. This process needs to be repeated at a frequency of approximately 80Hz. We need a device to send these values from a Linux computer to the 4 analog entries of the machine (0-10V, 0.5 mA) by coaxial BNC cable. We managed to do this for one channel using an USB connected oscilloscope by sending a continuous current by changing the offset using C++. The problem is that this solution is too slow and has only one channel. For this we would need a device that has a viable and fast connection (Ethernet, PCI, even USB if recommended) that can send data from a Linux computer (ideally using C++) with a latency of around 1ms, frequency of at least 100Hz, precision of 0.1% and on 4 synchronized analog outputs. Given that I am not particularly specialized in the field of electronics, researching such a device among the large quantity of items produced by your firm proves to be a difficult task. I would like to know if you have a product that fits our needs and if similar purpose programming has already been done (or could easily be done) to send data from a linux computer to analog outputs (using C++ ideally). Best regards, Ionut Prisacari
  17. Hi, I was working with the PmodDA4 to get it up and running, but was having trouble to get it to work since I didn't know how the 32 bit Word the reference manual claimed I needed to send was supposed to look like.
  18. Hello! If you have ever used something that produced sound through a speaker, than you have indirectly used a Digital-to-Analog Converter, or DAC for short. Many tutorials on how to use a DAC will cover how to use a R-2R resistor ladder which is one of the popular ways that DACs are constructed. However, not very many explain how you might use a DAC that is already created in a small IC chip, such as the one present on the PmodDA4. But no more! You can learn more about DACs in general from the Digilent Blog as well as how to use an IC DAC from this Instructable.