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Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect Pmod DA3 clock to XADC clock creating a unique clock for the entire design. This design was validated. Creating a HDL Wrapper, it has a correct synthesis, implemetation and bitstream. Programing the board i dont get any analog value for output Pmod DA3, it only works output LED[15:0]. Modules works correctly independently. Should i make a different connection for clocks? I dont know if there is a clock problem or other type problem. i attach the project Can anyone help me? Thanks! XADC + DA3.rar
We have a couple of DA3 modules connected to a pair of Xilinx Spartan 3 FPGAs. We are generating an audio ferquency baseband signal with at 200 ksps. Looking at the buffered output from the module we periodically see a sub-1us 500uV pulse approximately every 100 samples when outputting a small signal sinewave. Offsetting our sinewave by different amounts can make the problem either better or worse. The datasheet for the AD5541 DAC talks about a 'Digital-to-analog glitch impulse' that seems to explain our unwanted pulse. We have crudely filtered out this pulse with an 18pF cap from the DAC output to GND. This does not seem to cause any problems at our relatively low baseband frequency. Is there an accepted method of dealing with these unwanted pulses? Would it be possible to add a position on the Pmod board for a filter to be added?