Search the Community

Showing results for tags 'd@n'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 7 results

  1. Mukul

    Data compression

    I'm working on Data compression so studying different code techniques such as follows to implement on zybo board Golomb coding special case Rice code compression Huffman code Arithmetic code And finally Dynamic Markov compression I selected DMC because it is dynamic in nature and work well with sensor (as input).Here is the problem that i don't know exactly markov compression is good for this or not. Also when i study the DMC it's algorithm is similar to sequence detector (so are they same?). Secondly in video processing/image processing or in general which tech. Is used in Data compression.
  2. FR

    Passing FFT result to DDS

    Dear All - I successfully implemented FFT after help and guidance ( ) .Now i want to pass the detected frequency to DDS ( My goal is to re-generate the detected frequency (FFT bin ) using DDS ) . So i need your guidance. CORDIC IP core can be use ? or some thing else you suggested. BR FRK
  3. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] ) s_axis_data_tlast (I provide this signal from a counter which run upto FFT points) s_axis_data_tready [ output] s_axis_data_tvalid [coming from fifo] s_axis_config_tdata [ passed 0] s_axis_config_tready [ output] s_axis_config_tvalid [constant 1] m_axis_status_tready [constant 1] m_axis_data_tready [constant 1]
  4. Hi, I am working on a project in which i am using Pmod Bt2. Once i have connected Pmod BT2 with Arduino and give it 5 voltage and ground then after few minutes Pmod BT2 turn off and Now it's not turning on. What is the problem with it ? Is it burn due to 5 voltage or what happened with it? Regards, AQ
  5. hello how to give external input of recorded voice(be it like a songs or something else but should be recorded one) to zedboard to the xadc auxiliary pins for performing FFT on it do let me know.Previously my task was to give sine wave input to the xadc header through the frequency and signal generator and perform the FFT on it to generate the spectrum of sine wave below has the attachment of generating a sine wave spectrum on zedboard now instead of sine wave i should give some recorded voice as input to the xadc header .I could not find what could be an instrument and the type of cables and wires to give external input to xadc header to perform FFT on it do let me know please.
  6. how pipelined FFT is working from the xilinx FFT pdf if input data is loading and unloading data in memory then how stage1 radix-2 FFT is fed to stage-2 radix-2 FFT and where latency is stored ?how it is working?Do let me know as it is not much briefly explained in xilinx FFT pdf. in page:42 block diagram of pipelined streaming i/o as there is not much description about it do let me kow the working of each blocks of it. https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf
  7. hello, iam trying to capture the xadc output in vivado through ILA logic analyzer core and then wanted to send that output to the input of fft please do let me know how to capture the xadc signals in the ILA core The below is my design in vivado please do let me know im very new to vivado fft.rar