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how pipelined FFT is working from the xilinx FFT pdf if input data is loading and unloading data in memory then how stage1 radix-2 FFT is fed to stage-2 radix-2 FFT and where latency is stored ?how it is working?Do let me know as it is not much briefly explained in xilinx FFT pdf. in page:42 block diagram of pipelined streaming i/o as there is not much description about it do let me kow the working of each blocks of it. https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf
hello, iam trying to capture the xadc output in vivado through ILA logic analyzer core and then wanted to send that output to the input of fft please do let me know how to capture the xadc signals in the ILA core The below is my design in vivado please do let me know im very new to vivado fft.rar