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Found 7 results

  1. Hi, I am a new comer just start studying FPGA with Zybo Z7-20 with Vivado 2020.2 and Vitis 2020.2. Tutorial, Creating a Custom IP core using the IP Integrator (, is a good resource to study the Custom IP for the first time. I followed all the procedure and got to succeeded exporting the hardware by going to File -> Export -> Export Hareware.... Of course, I included bitstream when exporting. Then I select File -> Launch SDK. I choose "C:\FPGAprojects\ZYBO_
  2. i am a new bee creating simple axi adder with help of the video but i am getting module adder not able to found can any one help me
  3. I'm trying to integrate a custom IP module (AXI4 peripheral) with the Vivado IP Integrator flow on the Arty-A7 board. I've followed the tutorial outlined here: I am able to successfully generate a bitstream - my PWM signals should be wired out to the PMOD JB connector. However, nothing works once I try to launch an application from within SDK. Even something as simple as "Hello World" fails to run. The board support package, libraries, and applications all compile without issu
  4. jello_cat

    Arty with custom IP

    I have Arty A7-35T and I tried following this tutorial ( to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.
  5. Hello, I downloaded the verilog source files for a H.264 Decoder from; I'm trying to integrate this decoder into a video pipeline on a Digilent Zybo board. However, when I try to package this IP in Vivado 2016.2, the GUI shows there is no ports. I'm able to successfully package it, but it is useless because there is no i/o. I've attached a few pictures from the Create and Package IP wizard to illustrate what I'm talking about. If I click the port import dialog, as shown in the picture, nothing happens. Does anyone have any suggestions as to how I can successfully impor
  6. vc26

    VHDL read from BRAM

    Hi, I have a block design with a microblaze, a BRAM, and a custom ip (VHDL). With the custom IP, I have 4 separate signals that will read at the same time from 4 consecutive rows in the bram and output the values. I'm having trouble figuring out how to read 4 separate signals from a single BRAM at the same time. Any advice is much appreciated. Thanks, Vic
  7. 1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits. 2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side?? kindly help me I'm beginner to vivado model based design. i have build design as per the image attached on addition to this, i want to add the above features to it as