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Found 4 results

  1. Hi all, I'm trying to connect a MIPI camera (Rpi camera v2) to the Digilent Nexys-4 DDR board through the JXADC connector. Since these pins are routed for differential signaling, the JXADC connector seemed the best option for this, but I soon ran into a couple of problems though: - the JXADC pins are not connected to any clock input pins on the Artix-7, so I get placement errors when trying to connect the MIPI clock lane to these pins. I found out there is only 1 P-version clock input pin available on all the PMODs, namely JB10 (which connects to H16 on the Artix-7), so I tried using JB10 & JB3 (N-version clock input) for the MIPI clock lane pair. I realize this pair will not be optimally routed for differential signaling, but it's the only option I can find. - the JXADC pins all connect to bank 15 on the Artix-7, which is the same bank as the DIP switches and LEDs. This gives errors when trying to use LVDS_25 on the JXADC pins, while also using the DIPs and/or LEDs, since they are LVCMOS33 and you can't have 3.3V as well as 2.5V on the same bank. Then I've seen a couple of posts on this forum from zygot, stating there are a lot of problems with this, which got me a little spooked. I didn't understand ALL of what is said on his posts, so the question I would like to ask here is: Is it at all possible to connect a camera with MIPI CSI-2 interface (2 data lanes, 1 clock lane) to the Digilent Nexys-4 DDR board or shouldn't I bother trying to get it work? I already constructed a small PCB following to the Xilinx XAPP 894 application note to make a D-PHY compatible connection to the Artix-7 pins, but now I'm afraid the board itself won't allow it. I've already spent some time on this, so I just want to make sure I'm not wasting any more time if it is not at all possible. Thanks in advance for your expertise. Koen
  2. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: CSI-2 Camera: DLP 2000 RGB - projector: HDMI projector: Display : Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................
  3. Hi all, I have a Zybo and have been using it successfully for a variety of HDMI / VGA video projects. I'd like to have a go at interfacing a Raspberry Pi V2 camera. I understand that I need to implement a MIPI CSI-2 receiver in VHDL and I have a reasonable idea of how to proceed. This may take a bit of effort, but that's part of the fun! However, what I'm not sure about is whether I can specify the appropriate 1.2v IO Standard that's required on the Zybo board via the high speed PMOD ports? Or, will I need to buy one of the newer Zybo-Z7 boards? I realise that the newer Zybo-Z7 boards have a 2 lane MIPI connector (which is very convenient), so I'm assuming that the connected Zynq pins can run in the appropriate 1.2v differential IO Standard. But for this to work does the newer Zybo-Z7 have a specific 1.2v VCC supply to facilitate this? (that perhaps the Zybo doesn't have) I will probably upgrade to the newer board anyway, but would like to understand if this is possible on the older Zybo. Many thanks!
  4. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)" "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first." Using VHDL and Vivado, how do I create logic to successfully read data from this sensor? I have the following code written (with notes/questions) but I'm pretty sure its wrong. It was put together based on my limited understanding and reading various other source code that perform similarly: I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value. If it is 1, increment the delay value. This way the delay should always be within +/- 1 of the ideal value. I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute). This is probably due to random chance. Really need help on this one!