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Found 1 result

  1. Hello, I am a fairly new to using the Basys 3 and a student using it for a project. I am attempting to output 4 separate variables from the Pmod ports on the board using the JA Pmod part. When I run synthesis, implementation, and then bitstream, I get the same error for all but one of my outputs. My error message: [Common 17-69] Command failed: Site cannot be assigned to more than one port ["D:/LogicLab/SignalsProjectMK1/SignalsProjectMK1.srcs/constrs_1/new/BasysOut.xdc":16] Constraint: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ##Pmod Header JA ##Sch name = JA1 set_property PACKAGE_PIN J1 [get_ports {o1}] set_property IOSTANDARD LVCMOS33 [get_ports {o1}] ##Sch name = JA2 set_property PACKAGE_PIN L2 [get_ports {o2}] set_property IOSTANDARD LVCMOS33 [get_ports {o2}] ##Sch name = JA3 set_property PACKAGE_PIN J2 [get_ports {o3}] set_property IOSTANDARD LVCMOS33 [get_ports {o3}] ##Sch name = JA4 set_property PACKAGE_PIN G2 [get_ports {o4}] set_property IOSTANDARD LVCMOS33 [get_ports {o4}] (o1-o4 are my 4 variables I want to output) Is my constraint file the cause of this error, and if so, how do I go about correcting my mistake? Thank you for the assistance.