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  1. I wanted to try the example Audio-DMA project but it went really bad. This is what I did and the output from Vivado and SDK 2017.4. Source the make_project.tcl. Update the ip because I must. Get eight critical warnings, e.g., [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . Generate output products. Generate HDL wrapper so I can extract the hardware. IIC ports names differ in the .xdc so I have to change them to capital letter (IIC). Also notice that the ja ports are there, I don't know why though. Generate the bitfile. Got 1715 warnings, mostly unconnected ports. Also about some unused sequential elements removed which can be bad. Export hardware with bitfile. Launch SDK and import 'Existing Projects into Workspace', i.e., the 'sdk' subfolder which yielded this; I see this in the guide; Many apparent errors at this stage can be solved by right-clicking the bsp project and selecting Re-generate BSP Sources. Ok, try; I can open the file in any text editor but SDK just shows a big red sign and 'Failed to create the part's controls'. There is also a small textbox where I can almost scroll around and see the content. In the problems tab I see this; If I comment that include out, this is shown instead; And that path do indeed not exist. Probably because that path does not exist, so doesn't the cpu_cortexa9 2.3 either. What can I possibly have done wrong, and what are all these Java errors? Is this something I should ask Xilinx about instead? Also, before this I tried the DRAM test program as a first thing. It failed so I thought I would just try something else in the meanwhile and this is what I got. Bad start for a new board =\.