Search the Community
Showing results for tags 'cpu'.
I'm writing a cpu on Nexys 4 DDR, but I have a problem: The DDR2 memory on Nexys4 will be reset whenever a new .bit file is written to the FPGA. I have already generated two .bit files. One is to write instructions and data to the DDR2 memory, and the other is the cpu program. What should I do to make the DDR2 memory remain the same even after it's programmed? Thank you!