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Found 9 results

  1. Hello, I have recently purchased the Analog Discovery 2 unit and I would like to easily obtain an accumulated count value in the logic analyzer. Is this something that is available within the software or is a custom script required? If this requires custom setup or script programming, can you point me to the documentation or project that I can view?? I appreciate any help...Thank you
  2. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am
  3. Greetings. I just started out VHDL not long ago,and not quite familiar with Moore FSM. So I was trying to write this Moore FSM code as shown in Picture of my initial sketch(Link to imgur,safe to click). after search for some reference about Moore in VHDL,I'm still stuck. I'm hoping someone can help me fill-in the missing pieces of my code and to fit into the sketch. Sincerely Appreciate. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity M6B is Port ( clk : in STD_LOGIC; x : in STD_LOGIC;
  4. Hi guys, I am new to this Forum. I am working with LabVIEW, cDAQ, NI 9361. I am trying to acquire the Pulse Signal output from a Flow meter (Flow meter Output: Passive open collector, 30V, 250mA) using NI 9361 and cDAQ 9185. Initially I connected flow meter output +24 and -25 directly to an oscilloscope, I couldn’t see any pulse. And Just tried connecting to PFI0+- of NI 9361. My program is as attached below. The counter started counting but after few minutes it was displaying 0 forever. The pulse details are Pulse width: 100ms and Pulse value: 1kg Max Range of flow is 36000kg\h
  5. For the past 3 weeks i have been fiddling around a bit with zybo even though i have just found out about what an fpga is using vivado i have made some simple projects like a full adder using vhdl source code and hardware manager, an AXI IP block that can output PWM for given DUTY and Frequency/Period input. But now i have hit a stand still in my new IP design, i need two counters that run simultaneously one will be a clock running at 50Mhz and the other will be catching the input signal the block gets and counting it. My main problem is if i put both counters in the same process are they
  6. I seem to be having trouble getting the AD2 to trigger on a repeated pulse. If I trigger on the edge of DIO 7 then it triggers OK (see logic_trigger_simple), problem is that power up sends spurious signals sometimes and so I'm tring to pulse on the counter. I have the counter set up as the other screenshot but it just will not trigger like that. There is no reset so I've set reset to DIO 15 which is unused and tied to ground. How can I get this to trigger on the number of pulses. Also, in the protocol triggeringl, is there any way to trigger on a sequence of hex val
  7. Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?
  8. Hello, I am trying to program my Basys3 with a simple counter, that will count a sequence, per the push of one of the push buttons on the board. I cannot get the implementation to run, correctly, and i have attached my port assignments, as well as the error message. The whole project is attached as well, and my code is below. Thanks, Mike Code: library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity maina is port ( --Btnc : in std_logic; Clk : in std_logic; ClrN : in std_logic;
  9. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE.