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Found 9 results

  1. Hello everybody, I am having a problem with the binary counter v12.0 reset SCLR signal, when implementing the Xilinx University Programme, Lab9 Project 3.1, 2015x (1). Environment: OS: Linux (Arch Linux) Xilinx Vivado 2018.3 Digilent Basys3 develoment board Verilog HDL Problem description: The project works as expected (counts up to 5 minutes, 0,1 second resolution), the exception is the counter reset button (BTNC, U18) is pressed it only stops the counting, when released, the counter is not reset, instead it keeps counting where it stopped. I am using the Vivado IP Catalog for generating the clock signal and the 4 binary counters(2) used on each 7-Segiment display digit. The Verilog code and constraint file are attached. The binary counter configuration: Implementing using: Fabric Output width: 4 [3:0] Increment Value (Hex): 1 Restrict Count (Hex): 4, 5, 9, 9 (7seg from left ro right) Count Mode: UP Clock Enable (CE): Checked Synchronous Clear(SCLR): Checked Init Value:(Hex): 0 Synchronous Controls and Clock Enable(CE) Priority: Sync Overrides CE Latency Configuration: Manual, 1 Feedback Latency Configuration: Manual, 0 I suspect I am overseeing/forgetting somewhere a simple detail. Any help/clarification is appreciated. Cheers, Rafael. (1) https://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2015x/Verilog/docs-pdf/lab9.pdf (2) https://www.xilinx.com/support/documentation/ip_documentation/counter_binary/v12_0/pg121-c-counter-binary.pdf lab9_3_1.v Basys-3-Master.xdc
  2. Hello, I have recently purchased the Analog Discovery 2 unit and I would like to easily obtain an accumulated count value in the logic analyzer. Is this something that is available within the software or is a custom script required? If this requires custom setup or script programming, can you point me to the documentation or project that I can view?? I appreciate any help...Thank you
  3. Greetings. I just started out VHDL not long ago,and not quite familiar with Moore FSM. So I was trying to write this Moore FSM code as shown in Picture of my initial sketch(Link to imgur,safe to click). after search for some reference about Moore in VHDL,I'm still stuck. I'm hoping someone can help me fill-in the missing pieces of my code and to fit into the sketch. Sincerely Appreciate. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity M6B is Port ( clk : in STD_LOGIC; x : in STD_LOGIC; rst : in STD_LOGIC; --z : out STD_LOGIC_VECTOR (6 downto 0); AN : out STD_LOGIC_VECTOR (1 downto 0); ledout : out STD_LOGIC_VECTOR (6 downto 0)); end M6B; architecture Behavioral of M6B is type state_type is (s0,s1,s2,s3,s4,s5); signal state : state_type; signal ledbcd : std_logic_vector (3 downto 0); signal ledonc : std_logic_vector (1 downto 0); signal osc : STD_LOGIC_VECTOR (24 downto 0); signal refresh_counter: STD_LOGIC_VECTOR (16 downto 0); signal oscen : std_logic; signal dispn : std_logic_vector (6 downto 0); begin process (clk,rst) begin if rst = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0 => if x = '0' then state <= s1; else state <= s0; end if; when s1 => if x = '0' then state <= s2; else state <= s1; end if; when s2 => if x = '0' then state <= s3; else state <= s2; end if; when s3 => if x = '0' then state <= s4; else state <= s3; end if; when s4 => if x = '0' then state <= s5; else state <= s4; end if; when s5 => if x = '0' then state <= s0; else state <= s4; end if; end case; end if; end process; process (state) begin case state is when s0 => AN <= "10"; ledout <= "0000000"; when s1 => AN <= "10"; ledout <= "0000111"; when s2 => AN <= "10"; ledout <= "0000000"; when s3 => AN <= "10"; ledout <= "1001111"; when s4 => AN <= "10"; ledout <= "0000000"; when s5 => AN <= "10"; ledout <= "0000111"; end case; end process; end Behavioral;
  4. Hi guys, I am new to this Forum. I am working with LabVIEW, cDAQ, NI 9361. I am trying to acquire the Pulse Signal output from a Flow meter (Flow meter Output: Passive open collector, 30V, 250mA) using NI 9361 and cDAQ 9185. Initially I connected flow meter output +24 and -25 directly to an oscilloscope, I couldn’t see any pulse. And Just tried connecting to PFI0+- of NI 9361. My program is as attached below. The counter started counting but after few minutes it was displaying 0 forever. The pulse details are Pulse width: 100ms and Pulse value: 1kg Max Range of flow is 36000kg\h. Then through the flowmeter manual found the connections for configuring Passive output as attached below. Applied this and could see the pulses on Oscilloscope (Red one channel A) And went through the NI9361 Manual and realized the connections for open collector output to be as file attached as NI open collector But, my flow meter doesn’t have separate pin for Vin and GND. It has only pin no +24 and -25. So connected Vout to +24 and then +24 to DI0+. -25 to DI0- and to ground. And created a task to test. But the counter output remained always Zero. Also tried connecting the ends +24 and -25 without Vsup to the NI card. But providing supply externally and the pulses were visible on oscilloscope. But, then the output was zero. In short, with no external power supply, I could see some random counts in LabVIEW but nothing on oscilloscope and with external power supply, I could notice pulses on oscilloscope and nothing on LabVIEW Panel Please suggest me to get the flow meter readings Thanks in advance Best Regards Deepa Mass flow rate in kg per h.vi
  5. For the past 3 weeks i have been fiddling around a bit with zybo even though i have just found out about what an fpga is using vivado i have made some simple projects like a full adder using vhdl source code and hardware manager, an AXI IP block that can output PWM for given DUTY and Frequency/Period input. But now i have hit a stand still in my new IP design, i need two counters that run simultaneously one will be a clock running at 50Mhz and the other will be catching the input signal the block gets and counting it. My main problem is if i put both counters in the same process are they still as sensitive, and if they are not how can i trigger the other counter without getting a Multi-driven net error when one reaches the limit i want if they aren't in the same process(like one counter counts as a clock and gives me the info about the other clock in 10 ms intervals, in a way an encoder would.)
  6. I seem to be having trouble getting the AD2 to trigger on a repeated pulse. If I trigger on the edge of DIO 7 then it triggers OK (see logic_trigger_simple), problem is that power up sends spurious signals sometimes and so I'm tring to pulse on the counter. I have the counter set up as the other screenshot but it just will not trigger like that. There is no reset so I've set reset to DIO 15 which is unused and tied to ground. How can I get this to trigger on the number of pulses. Also, in the protocol triggeringl, is there any way to trigger on a sequence of hex values, rather than just one - if not in the main software - can this be done with the SDK? Thanks, Matt
  7. Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?
  8. Hello, I am trying to program my Basys3 with a simple counter, that will count a sequence, per the push of one of the push buttons on the board. I cannot get the implementation to run, correctly, and i have attached my port assignments, as well as the error message. The whole project is attached as well, and my code is below. Thanks, Mike Code: library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity maina is port ( --Btnc : in std_logic; Clk : in std_logic; ClrN : in std_logic; Q : out std_logic_vector (2 downto 0)); end maina; architecture BEHAVIORAL of maina is signal Qint: std_logic_vector (2 downto 0); begin process(Clk) begin if Clk' event and Clk = '1' then if ClrN = '1' then Qint <= "000"; elsif ClrN = '0' then case Qint is when "000" => Qint <= "110"; when "110" => Qint <= "111"; when "111" => Qint <= "100"; when "100" => Qint <= "101"; when "101" => Qint <= "001"; when "001" => Qint <= "000"; when others => Qint <= "000"; end case; end if; end if; end process; Q <= Qint; end behavioral; Lab5_LUT_mod4.xpr
  9. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE. http://m.instructables.com/id/How-to-use-Verilog-and-Basys-3-to-do-3-bit-binary-/