Search the Community

Showing results for tags 'constrant file'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here is my constraint file: # Clock Source - Bank 13 set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK" # ---------------------------------------------------------------------------- # User LEDs - Bank 33 set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0" set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1" set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2" set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3" set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4" set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5" set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6" set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7" # User Push Buttons - Bank 34 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC" set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND" # ---------------------------------------------------------------------------- # User DIP Switches - Bank 35 # --------------------------------------------------------------------------- set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0" #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" # --------------------------------------------------------------------------- # IOSTANDARD Constraints # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]]; # Set the bank voltage for IO Bank 34 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; # Set the bank voltage for IO Bank 35 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF]; My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better. Part#: xc7z020clg484-1 or ****-2 getting the same result. I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program". Please refer to images and let me know if I am not clear enough. Thank you for your helps in advance.
  2. Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the sw_led.v file and a Basys3_sw_Demo.xdc constraint file. After downloading the files, building the project, then running the synthesis I get 26 critical warnings that cause the Implementation and Generate BitStream to fail. 22 of the critical warnings are "V17 is not a valid site or package pin name" (and each of the following 21 warnings change the "V17" to the next pin name in the constraint file. (I've checked the schematic and the Pin Names ARE VALID) The next critical warning is "Setting property "IOSTANDARD' is not allowed for GT Terminals and this error is flagging only a single line in the constraint file yet ALL of the switches in the constraint file all do a "set_property IOSTANDARD LVCM0S33......... The final 2 critical warnings are "Cannot set LOC property of ports. Site location is not valid. This error is flagging two of the LED settings in the contraint file yet, once again, all 16 of the LED's are using the same commands within the constraint file. I'm at a brick wall trying to figure out what the heck the problem is here. As I said...the 1st Tutorial went fine. This tutorial even included the constraint file needed for the project. I've attached a zip file containing the entire Vivado project. Any help/advice would be greatly appreciated. THANKS! project_2.zip