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Showing results for tags 'constrant file'.
Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here
Hi all: I'm new to both Vivado and the Basys3 board. I've been working thru the initial tutorials to get myself familiar with the software and the board. The very 1st tutorial, Getting Started with Vivado, went fine. Everything worked as advertised. The problem I've run into is with the 2nd tutorial, Basys 3 Programming Guide Tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-programming-guide/start). I have the latest version of Vivado (2018.3) and the tutorial was built with 2015.1. The tutorial even has a zip file to download both the s