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Found 5 results

  1. SeanS

    Genesys 2 DDR Constraints

    Hello, I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here: https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc But there doesn't appear to be any constraints for the DDR3. I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- #  For DDR constraints please refer to our website #_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- Where can I find the pin, level, and timing constraints for the DDR3 peripheral interface? -Sean
  2. Hello, I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning: [Timing 38-282] The design failed to meet the timing requirements. According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D" with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787. Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning? I tried this on three different machines, always getting the same critical warning. Eff
  3. Hi I am currently working on a project in Vivado 2017 using the external mux. I have more of a general question concerning the constraints file (.xdc). How does one go about creating their own xdc file? Normally, do you start with the full zedboard constraints file and comment things in yourself or can Vivado create one for you? Also is there a place I can look that explains the complete constraints file for the Zynq 7000 and when to use them? Thanks Sam
  4. Hi all, I'm currently working on a project for the Oculus Rift, where I need to generate HDMI ouput. Currently I'm using an rbg2dvi IP block to generate TMDS-output, however, when I assign the correct pins in the constraints file by uncommenting the TDMS_clk and TDMS_Data pins, the implementation gives a critical warning about not knowing the I/O standard TDMS, even though it is specified as that in the default constraints file. I'm also already using the latest board files in Vivado 2016.1 Is there anyone who can help me with this issue? Regards, Niels
  5. Hi, I am implementing in Vivado the Arty's Microblaze based design that Adam Taylor posted on his website: http://adiuvoengineering.com/?p=626I I am having problems with it: Synthesis ran without any high importance warnings, but at the end of implementation I get three high severity warnings after I run the "Report Timing Summary": USB_UART_RXD: Port with no Input DelayUSB_UART_TXD: Port with no Input Delayddr3_sdram_reset_n: Port with no Output DelayI do not know how should I constrain these inputs and outputs. (Note: My Arty environment is working ok (board files have been downloaded and installed). I already have ran some basic logic circuits in the ARTY board successfully. My problems started with this project that includes the Microblaze and the uart) Attached are the snapshot of my block design (It is basically a copy of Adam Taylor's design) and a copy of the warnings I get. Let me know if I need to do something about these warnings, and if so, how, Thanks!