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  1. Dear All, I need to use inside the FPGA the 12 MHz clock, hence I've uncommented this two rows on the XCF file provided by Digilent. ## 12 MHz Clock Signal set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}]; after that I've did the sysnthesis, my VHDL code is the following one: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led is Port ( btn : in STD_LOGIC_VECTOR(1 downto 0); led : buffer STD_LOGIC_VECTOR(1 downto 0); sysclk : in std_logic -- system clock 12 MHz ); end led; architecture Beh_arch of led is signal btn0s : std_logic; signal btn1s : std_logic; signal led0 : std_logic; signal led1 : std_logic; begin -- button clock synchr synch_input : process (sysclk) begin if sysclk'event and sysclk = '1' then btn0s <= btn(0); btn1s <= btn(1); end if; end process synch_input; -- led toggle with the button synch_toggle_leds : process (sysclk) begin if sysclk'event and sysclk = '1' then if btn0s = '1' then led0 <= not led(0); end if; if btn1s = '1' then led1 <= not led(1); end if; led(0) <= led0; led(1) <= led1; end if; end process synch_toggle_leds; end Beh_arch; what I try to do is a simple toggle of the led when the button is pressed, countinuosly toggling at the clock frequency. All the process going straight but on the final report I see a warning: [DRC 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. I've did some search and I found this: someone could you please give me some other explanation? What should be the exact settings to use for this board: - Configuration voltage: 1.5 / 1.8 / 2.5 / 3.3 - Configuration bank voltage selection: GND or VCCIO where I can found this specification for the FPGA used? Datasheet I think but what parameters? ---- I've noticed the last row "Refer to the device configuration user guide for more information" then found the UG470 (v1.12) at page 21 and 24 Table 2-4 there are some infos. Searching for the pin-label file give me () V9 and G12 -> VCCO_0 V11 -> CFGBVS_0 After that searching on the electrical schematic give me: 3.3 V VCCO_0 (page 4/7) 3.3 V CFGBVS_0 (page 2/7) Then following these data, the correct settings should be as into the attached figure (select first the Syntesis tab into the left side of the Vivado main window then into the main Vivado menu bar select Tools tab and finally the Edit Device Properties menu). After that the warning disappear and the board is also running correctly as before the warning :). Someone can confirm? Thanks! Best regards